32 Commits

Author	SHA1	Message	Date
Cedar Turek	e994f26d6d	simplified initU and UM logic, separated radix2/4 logic	2022-12-30 18:57:07 -08:00
Cedar Turek	ba90d868db	took out broken muxes	2022-12-30 15:13:52 -08:00
Cedar Turek	545a3ff363	various cleanup	2022-12-30 14:31:23 -08:00
David Harris	dfc0b5d1ad	Removed MDUE from unnecessary places in fdivsqrt	2022-12-27 10:42:40 -08:00
Cedar Turek	bebaf08bed	took out otfc swap. updated postprocessing quotient/remainder logic for int div.	2022-12-26 21:03:56 -08:00
David Harris	9e21358d75	Removed unused signals from FPU	2022-12-23 00:18:39 -08:00
David Harris	0a7ed944a5	Revert to 98b824	2022-12-22 23:58:14 -08:00
David Harris	56312cd0a6	Clean up unused FPU signals	2022-12-22 23:53:09 -08:00
David Harris	4d509f94ec	FDIV merge	2022-12-22 23:03:03 -08:00
David Harris	2d72bed1f4	Removed unused signals in FPU and CSR	2022-12-22 22:59:05 -08:00
cturek	ccbad67497	Added negative-result int diviison support in U and UM registers. 13 tests pass!	2022-12-22 16:25:37 +00:00
cturek	c3fdc0ab23	Renamed signals to E and M stages, forwarded preprocessed n to fsm	2022-12-22 00:43:27 +00:00
Alessandro Maiuolo	2989782fe6	fixed LOGRK. FIxed Xs in WC and WS from muxes reliant on SqrtE. note not linting on 4 copies radix 4 because IntBits only 7 bits wide (need 8)	2022-12-18 19:04:36 -08:00
cturek	4b8cbd9fa0	Added integer support for initC	2022-12-16 19:02:11 +00:00
cturek	8829e627eb	Fixed BZero and initU/initUM muxes	2022-12-14 16:44:46 +00:00
cturek	f57211bb49	Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs	2022-12-10 21:56:35 +00:00
Ross Thompson	de99663b97	Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." ... This reverts commit 70b89e5214.	2022-12-04 00:01:58 +00:00
cturek	70b89e5214	Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.	2022-12-02 21:44:29 +00:00
David Harris	d64cd715f9	Renamed DivStartE to IFDivStartE	2022-12-02 11:30:49 -08:00
David Harris	9c1b7e53e4	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
David Harris	ddba68605e	Renamed DivBusy to FDivBusyE in FPU	2022-11-16 10:13:27 -08:00
cturek	b137a95a35	propagated otfc swap to Rad2 and 4 qslc	2022-11-06 23:32:38 +00:00
cturek	1e927df1a0	Added conditional OTFC swap for simplified int postprocessing	2022-11-06 23:09:09 +00:00
cturek	51fc4de0e1	small signal cleanup	2022-10-26 18:42:49 +00:00
David Harris	dceb6f9034	Moved shift into divsqrt stage and cleaned up comments	2022-10-09 04:45:45 -07:00
David Harris	55e4911cf0	fdivsqrt code cleanup	2022-10-09 03:37:27 -07:00
David Harris	fc4146f409	Adding start signals for integer divider to fdivsqrt	2022-09-29 16:30:25 -07:00
David Harris	cfa83fdd98	For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc	2022-09-21 13:30:35 -07:00
David Harris	811f498f63	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
David Harris	705a2bd97b	Removed D2 and D2b from radix2 stage	2022-09-20 04:20:38 -07:00
David Harris	c77ec2aa9c	Simplified UM initialization	2022-09-20 04:18:12 -07:00
David Harris	8d1408a9d6	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00