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Author SHA1 Message Date
Noah Limpert
73cca666bf Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
David Harris
870c15c4f5
Update README.md 2023-04-20 14:15:34 -07:00
David Harris
5f14dfe748
Update README.md 2023-04-20 14:09:32 -07:00
Ross Thompson
ffa686a605
Merge pull request #264 from davidharrishmc/dev 
Added -fp flag to run arch64d/f tests in coverage
 2023-04-20 09:26:16 -05:00
David Harris
9fac2b6e57 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-19 14:50:09 -07:00
David Harris
24e60c232d
Merge pull request #262 from SydRiley/main 
removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
 2023-04-19 14:49:50 -07:00
Sydeny
039a06ec95 clarifying comments in exclusions 2023-04-19 14:47:34 -07:00
Sydeny
b76ed145e6 removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98% 2023-04-19 13:30:12 -07:00
David Harris
a3f3967f59 Added -fp flag to run arch64d/f tests in coverage 2023-04-19 13:07:07 -07:00
David Harris
a4cc3c6b3e
Merge pull request #261 from liamchalk00/main 
Add pmpcfg test cases increasing IFU coverage
 2023-04-19 12:37:19 -07:00
Liam
2684a81754 Add pmpcfg test cases increasing IFU coverage 2023-04-19 11:58:22 -07:00
Ross Thompson
a6903ac5f3 Yeah We boot linux on the arty a7! 2023-04-19 11:17:33 -05:00
Ross Thompson
c463bd8cdd Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram. 
but the data is wrong.
 2023-04-19 10:35:18 -05:00
David Harris
68295bd750
Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
5ac756b685
Merge pull request #259 from AlecVercruysse/coverage4 
D$ Coverage
 2023-04-19 06:17:01 -07:00
David Harris
79dbfae4af
Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
c36d3cb32b
Merge pull request #258 from liamchalk00/main 
Add test cases for pmpcfg.S
 2023-04-19 04:52:59 -07:00
David Harris
59d153ace0
Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
2beb32e6b9
Merge pull request #257 from koooo142857/main 
PMPCFG_ARRAY_REGW cases
 2023-04-19 04:47:12 -07:00
David Harris
a13feb5d0b
Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
David Harris
f4a949c28c
Merge pull request #255 from kjprime/main 
Add PR#252 test file to coverage
 2023-04-19 04:43:25 -07:00
Alec Vercruysse
7ba2bfd4b6 CacheFSM logic simplification for AMO operations 
Ran this by Ross.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae D$ scope-specific coverage exclusions (I$ logic that never fires) 
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.

Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.

There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
e3593800d9 fix unhit exclusion in fdivsqrtfsm 2023-04-19 01:34:01 -07:00
Liam
2a4bc01944 Update tests.vh 2023-04-18 23:15:47 -07:00
Liam
777028e43b Add test cases for pmpcfg.S 2023-04-18 23:06:52 -07:00
Kevin Wan
fe51108740 a 2023-04-18 22:09:50 -07:00
Kevin Wan
fed7681695 Merge branch 'main' of https://github.com/koooo142857/cvw into main 2023-04-18 21:55:06 -07:00
koooo142857
ea39b53c97
Merge branch 'openhwgroup:main' into main 2023-04-18 21:53:46 -07:00
Kevin Wan
20a0803f46 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
3ef81f4e6a PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Cedar Turek
30bd1e2a33 created fdivsqrtcycles, moved cycles calculation from FSM to preproc 2023-04-18 16:14:45 -07:00
Kevin Thomas
385564fe4c Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00
Ross Thompson
d783456746 Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. 2023-04-18 17:45:41 -05:00
Cedar Turek
871d495ca1 gave integer bits to D instead of adding manually everywhere 2023-04-18 15:41:04 -07:00
Cedar Turek
054c8d638c moved D flop to preproc 2023-04-18 15:14:17 -07:00
Ross Thompson
bb4ebd9b61 More debug stuff. 2023-04-18 16:00:10 -05:00
Ross Thompson
667524efcb Added more signals to debugger in hopes I can figure out why the mig is not responding. 2023-04-18 15:51:52 -05:00
Ross Thompson
2df6c6cb0f It's almost working. 2023-04-18 14:24:59 -05:00
David Harris
d5e2fefe2c
Merge pull request #252 from mcook26/main 
Increase of TLB coverage in IFU
 2023-04-18 05:49:18 -07:00
Miles Cook
5cfd0577d1 Increase of TLB coverage in IFU 2023-04-17 18:35:03 -07:00
Ross Thompson
ac95087042 Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
dd7f5310e4 Fixed timing constraint issue. 2023-04-17 19:53:43 -05:00
Ross Thompson
00c61fc5b3 Found the DDR3 memory is not ready when issuing the first store. 2023-04-17 19:33:13 -05:00
Ross Thompson
8bebc56b56 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. 2023-04-17 18:39:25 -05:00
Ross Thompson
8377ff8c51 Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. 2023-04-17 16:37:18 -05:00
Sydeny
f0ff1a4447 increasing lsu coverage by excluding the pmachecher/adrdecs/clintdec or uncoreram signal SizeValid becauseany size is valid so signal is always 1 2023-04-17 14:19:48 -07:00
Ross Thompson
96781e0b2a Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. 2023-04-17 16:00:02 -05:00