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Author SHA1 Message Date
Limnanthes Serafini
38349e6a4f Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 17:00:43 -07:00
Limnanthes Serafini
51f6561476 A couple indents->spaces 2023-04-13 17:00:41 -07:00
Noah Limpert
419377a8f8 git did not seem to add tests.vh, trying again 2023-04-13 16:59:10 -07:00
Limnanthes Serafini
1125bad9cb
Merge branch 'openhwgroup:main' into cachesim 2023-04-13 16:54:35 -07:00
Limnanthes Serafini
e33721fbe4 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
c427b4c896 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Limnanthes Serafini
ecce9b0ce1 Fix of InvalDelayed warning 2023-04-13 16:53:36 -07:00
David Harris
8db317133c Starting fdivsqrt cleanup 2023-04-13 16:53:33 -07:00
Sydeny
1dab409bae Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Ross Thompson
679dc7d73b Progress on arty a7 board. 2023-04-13 17:57:12 -05:00
David Harris
56686e9475
Merge pull request #241 from Dygore/main 
Added a test for denormalized FP numbers
 2023-04-13 15:31:50 -07:00
Noah Limpert
98420e45ac update tests.vh, add tlbKP to load all lines of tlb 2023-04-13 15:13:55 -07:00
Dygore
3d5c128470 Added a test for denormalized FP numbers 2023-04-13 16:39:27 -05:00
Noah Limpert
3a06ec7094 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 
pull in changes to trap handler so that permissions should change correctly
 2023-04-13 12:34:27 -07:00
David Harris
892d6a4bcd
Merge pull request #239 from ACWright256/main 
Fixed exception handling to handle ecalls properly
 2023-04-13 09:32:56 -07:00
Alexa Wright
f8a8c43307 Fixed exception handling to handle ecalls properly 2023-04-13 09:23:32 -07:00
Sydeny
6f308e85ed Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-12 16:20:50 -07:00
Alec Vercruysse
a52eb01407 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
92cd0cb6ab track GetLinenum.do (tcl procedure to find line numbers to exclude) 2023-04-12 15:58:38 -07:00
Alec Vercruysse
a3d9e11b0f cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
Ross Thompson
29e68a82b2
Merge pull request #236 from stineje/main 
Modification to testfloat.do
 2023-04-12 17:40:04 -05:00
James E. Stine
4503ad4c87 Add simple example based on original C program built by David Harris for OSU who want to see easy way to convert FP numbers 2023-04-12 17:20:11 -05:00
Alec Vercruysse
800f0245f3 Cachefsm gate LRUWriteEn with ~FlushStage 2023-04-12 13:32:36 -07:00
Sydeny
e2520c8a27 fctrl coverage at 100% after removing redundancies from conditional statements 2023-04-12 13:07:30 -07:00
James E. Stine
dee4d49e42 Modification to testfloat.do to accept argument for nowave or by default none 2023-04-12 14:49:40 -05:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
Alec Vercruysse
e303d99d5b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
David Harris
44023e7ee7 Removed unnecessary start term from initialization muxes to simplify and improve coverage 2023-04-12 03:34:01 -07:00
David Harris
a433b8a1c1
Merge pull request #234 from AlecVercruysse/cachesim 
CacheSim: Logger improvements, performance logging, sim wrapper
 2023-04-12 03:14:03 -07:00
Limnanthes Serafini
e6269b364f Minor comments. 2023-04-12 02:57:42 -07:00
David Harris
3b6e397172 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
Limnanthes Serafini
978b475269 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
David Harris
28c02a7e6a Fixed fdivsqrt to avoid going from done to busy without going through idle first 2023-04-12 02:48:40 -07:00
David Harris
c5e3b5c68d Swapped in svadu mmu tests 2023-04-12 02:06:52 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
d60e3aaf53 only assign ClearDirtyWay for read-write caches 2023-04-12 01:15:35 -07:00
Alec Vercruysse
729f81a0df refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
1ce2ab5daa Coverage and readability improvements to LRUUpdate logic 
The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
214abc7006 Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE 
Some address options are only used in the D$ case.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
6dce58125b Remove FlushStage Logic from CacheLRU 
For coverage.

LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.

Update cache.sv to reflect cacheLRU edit.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
3fc6bb0c40 Exclude (FlushStage & SetValidWay) condition for RO caches 
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
 2023-04-12 01:15:35 -07:00
Ross Thompson
2f6ed64e26
Merge pull request #232 from stineje/main 
Mod testing for TestFloat
 2023-04-11 23:22:59 -05:00
James Stine
5d1ad53bc7 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00
James Stine
f5201da676 Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
Limnanthes Serafini
11a5b23bb8 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Limnanthes Serafini
fdb81e44c9 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Limnanthes Serafini
3f7f3d6a42 Wrapper for running CacheSim on the rv64gc suites 2023-04-11 19:29:05 -07:00
Limnanthes Serafini
b6ecd15eff Cleanup + success message added to CacheSim 2023-04-11 19:28:28 -07:00
David Harris
953518bcba Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-11 19:08:09 -07:00
David Harris
32daa34680
Merge pull request #231 from kipmacsaigoren/priv-tests 
Priv tests Updates for SVADU, and SAIL
 2023-04-11 19:07:13 -07:00