David Harris
e14eb9872e
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 12:33:59 -08:00
David Harris
d936342c97
Refactoring ALU and datapath muxes
2021-12-08 12:33:53 -08:00
Ross Thompson
8b7cefab79
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-08 13:40:44 -06:00
Ross Thompson
9ddd065340
Updated coremark testbench with the extra ports from FPGA merge.
...
Fixed coremark Makefile to create work directory.
2021-12-08 13:40:32 -06:00
bbracker
255cc26126
increase regression's expectations of buildroot to 246 million
2021-12-08 07:01:22 -08:00
slmnemo
7d614869a1
Removed .*s from wally-pipelined/src/uncore/uncore.sv
2021-12-08 01:03:02 -08:00
slmnemo
f413ea1b4a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-08 00:26:13 -08:00
Noah Limpert
15bdf5680e
removed .* instantiation from ieu.sv and datapth.sv in ieu folder
2021-12-08 00:24:27 -08:00
slmnemo
021faaf8cd
Removed .* from mmu instance inside lsu.sv.
2021-12-08 00:15:30 -08:00
Katherine Parry
80f026a734
FMA uses one LOA
2021-12-07 14:15:43 -08:00
bbracker
5a611bd82d
undo intentionally breaking commit
2021-12-07 13:43:47 -08:00
bbracker
5d90f899b8
intentionally breaking commit
2021-12-07 13:27:34 -08:00
bbracker
c9808988c1
undo intentionally breaking commit
2021-12-07 13:27:06 -08:00
bbracker
2b41e37160
intentionally breaking commit
2021-12-07 13:23:19 -08:00
bbracker
8f73c1df9e
2nd attempt at making regression-wally.py able to be run from a different dir
2021-12-07 13:13:30 -08:00
bbracker
979580b1e7
fix checkpointing so that it can find the synchronized reset signal
2021-12-07 13:12:06 -08:00
bbracker
302bc56646
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-07 11:16:51 -08:00
bbracker
010339fa05
attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly
2021-12-07 11:16:43 -08:00
Ross Thompson
4dbd5d45ee
Added information on how to copy the linux image to flash card.
2021-12-07 13:16:38 -06:00
bbracker
2229e66d6c
add buildroot tv linking to make-tests.sh
2021-12-07 11:15:59 -08:00
Ross Thompson
6c6b7865fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-07 13:12:59 -06:00
Ross Thompson
22721dd923
Added generate around the dtim preload.
...
Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
bbracker
5a73ecd0be
regression.py bugfix
2021-12-06 19:32:38 -08:00
bbracker
4df9093a7f
add make-tests scripts
2021-12-06 15:37:33 -08:00
bbracker
7c44ecb364
add buildroot-only option to regression
2021-12-06 14:13:58 -08:00
bbracker
524bb0aa9a
linux-testvectors symlinks shouldn't be in repo, especially not in this location
2021-12-05 22:03:51 -08:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
David Harris
f45fe48158
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-04 20:26:01 -08:00
David Harris
64f33161bc
Added files to repo
2021-12-04 20:25:33 -08:00
Skylar Litz
546f7fb4c2
fix some interrupt timing bugs
2021-12-03 12:32:38 -08:00
Ross Thompson
500e6ff430
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
b03ca464f1
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
9ccc8e7f3a
Merge branch 'fpga' into main
2021-12-02 14:28:10 -06:00
kwan
5164129172
.* resolved in ifu.sv
2021-12-02 10:32:35 -08:00
kwan
05a838aee2
.* in ifu/ifu.sv eliminated
2021-12-02 09:45:55 -08:00
David Harris
42780ba40b
Added coremark scripts to regression directory
2021-12-01 09:08:06 -08:00
David Harris
a146d7a618
testing push
2021-11-30 11:20:09 -08:00
Ross Thompson
97c73f10ff
Fixed uart for FPGA config after merge. This still needs some work.
2021-11-29 16:07:54 -06:00
Ross Thompson
a871118116
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
fed0bb08d6
UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
2021-11-25 11:01:59 -08:00
Noah Limpert
09d3322a26
updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well
2021-11-24 23:22:04 -08:00
Noah Limpert
93b626ce2a
replaced .* instation of priv module on wallypiplinedhart
2021-11-24 22:58:59 -08:00
Noah Limpert
f36cc7a2a3
Made abhlite instation on wallypipehart more clear, updated spacing for consistency
2021-11-24 22:48:01 -08:00
Noah Limpert
5b7c969170
updated module instation of LSU on wallypiplinedhard
2021-11-24 22:09:39 -08:00
bbracker
23194c0308
fix parseState.py to correctly take in PMPCFG
2021-11-24 16:52:51 -08:00
Ross Thompson
1183aed049
Missed another change to uart.
2021-11-23 10:20:47 -06:00
Ross Thompson
3fc370654d
Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
2021-11-23 10:00:32 -06:00
Ross Thompson
f12e7e1b68
Added QEMU hack for initial LCR value in uart.
2021-11-22 15:23:19 -06:00
