354 Commits

Author	SHA1	Message	Date
Ross Thompson	de868ef3a2	Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.	2022-04-07 16:56:28 -05:00
Katherine Parry	74e0db04ac	fixed errors and warnings in rv32e	2022-04-07 17:21:20 +00:00
Ross Thompson	900939581e	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-05 15:42:07 -05:00
Ross Thompson	5faa88acd5	Increazed fpga clock speed to 35Mhz. ... linux boot is much faster.	2022-04-05 15:09:49 -05:00
Katherine Parry	c3d07b2c46	generating all testfloat vectors	2022-04-04 17:17:12 +00:00
Ross Thompson	91e99f0d34	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-04 10:56:10 -05:00
Ross Thompson	077beb18dd	Constraint changes for 40Mhz wally.	2022-04-04 10:50:48 -05:00
Ross Thompson	b77201143f	Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.	2022-04-04 10:38:37 -05:00
Ross Thompson	400b5f7632	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
Ross Thompson	38160fe6ea	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-03 17:56:55 -05:00
David Harris	fb95767da0	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
Ross Thompson	3db60a1cc1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-02 16:39:54 -05:00
Ross Thompson	2376d66ec2	Added more ILA signals.	2022-04-02 16:39:45 -05:00
Ross Thompson	48c49802b2	Fixed linting issues.	2022-04-01 15:20:45 -05:00
Ross Thompson	301f20052b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-01 12:50:34 -05:00
Ross Thompson	19a8df9739	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
bbracker	e09079d8b4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 17:54:43 -07:00
bbracker	55df8bc3f7	fix lingering overrun error bug	2022-03-31 17:54:32 -07:00
Ross Thompson	48c862d536	Added PLIC to ILA.	2022-03-31 16:44:49 -05:00
Ross Thompson	da93d14050	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 16:30:55 -05:00
Ross Thompson	b5cdf035fc	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 15:50:04 -05:00
Ross Thompson	ade4a4cd5e	Notes on what to change in ram.sv.	2022-03-31 15:48:15 -05:00
bbracker	bdb3417656	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 13:46:32 -07:00
bbracker	0f7e995055	simplify plic logic	2022-03-31 13:46:24 -07:00
David Harris	c7043e4d63	Added SystemVerilog flag to fma.do so that fma16 compiles properly	2022-03-31 17:00:38 +00:00
Ross Thompson	88c5cdc873	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 11:39:41 -05:00
Ross Thompson	bf9683f0d2	Forced to go back to hard coded preload.	2022-03-31 11:39:37 -05:00
Ross Thompson	54001222cf	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 11:38:55 -05:00
Ross Thompson	285fc6fd4d	Modified clint to support all byte write sizes.	2022-03-31 11:31:52 -05:00
David Harris	dd3af17b3f	Added synthesis script for fma16	2022-03-31 00:51:33 +00:00
David Harris	3457c6e512	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-30 23:06:36 +00:00
bbracker	69a0f6e00b	big interrupts refactor	2022-03-30 13:22:41 -07:00
Ross Thompson	0a5b500aca	Changed sram1p1rw to have the same type of bytewrite enables as bram.	2022-03-30 11:38:25 -05:00
David Harris	9b1f85d353	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-30 16:26:27 +00:00
Ross Thompson	e4f4e1bd43	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-30 11:09:44 -05:00
Ross Thompson	f52ab01362	Partial cleanup of memories.	2022-03-30 11:09:21 -05:00
Ross Thompson	839bede656	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
Ross Thompson	997c1b87fe	rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.	2022-03-29 23:48:19 -05:00
Ross Thompson	66e9380cfb	Partial fix to allow byte write enables with fpga and still get a preload to work.	2022-03-29 19:12:29 -05:00
David Harris	03fa9084bc	Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv	2022-03-29 19:16:41 +00:00
David Harris	c4f2c6b110	fpu compare simplification, minor cleanup	2022-03-29 17:11:28 +00:00
Kip Macsai-Goren	56a0542405	made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes	2022-03-29 02:26:42 +00:00
bbracker	8ea25e591b	fix typo that Madeleine found	2022-03-28 15:39:29 -07:00
Kip Macsai-Goren	709f8e6e0d	fixed double multiplication on vectored interrupts	2022-03-28 19:12:31 +00:00
Ross Thompson	61c714ebe6	I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.	2022-03-25 13:10:31 -05:00
Ross Thompson	fe896bff8e	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
bbracker	d33de3ef6b	tabs vs spaces disagreement	2022-03-24 17:11:41 -07:00
bbracker	4b376e2834	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
Ross Thompson	71aad2d213	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
Ross Thompson	8f74fd2a50	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-23 14:10:38 -05:00