19 Commits

Author	SHA1	Message	Date
bbracker	5a661a7392	provide time and timeh CSRs based on CLINT's counter	2021-06-17 08:38:30 -04:00
Thomas Fleming	38236e9172	Implement first pass at the PMA checker	2021-04-22 15:34:02 -04:00
bbracker	368c94d4ff	working GPIO interrupt demo	2021-04-15 21:09:15 -04:00
bbracker	31c6b2d01f	Yee hoo first draft of PLIC plus self-checking tests	2021-04-04 06:40:53 -04:00
bbracker	11d4a8ab34	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Noah Boorstin	a2b0af460e	everyone gets a bootram	2021-03-18 12:35:37 -04:00
bbracker	850a2e9329	added a delay to sel signals	2021-03-05 15:07:34 -05:00
bbracker	77e2e357a7	more merging fixes	2021-03-05 14:36:07 -05:00
bbracker	ed4ff1ecd0	remove deprecated mem signals	2021-03-05 14:27:38 -05:00
bbracker	0f4a231543	first merge of ahb fix	2021-03-05 14:24:22 -05:00
Noah Boorstin	dfae278ffb	busybear: make imperas tests work again	2021-03-04 22:44:49 +00:00
Noah Boorstin	4833b36535	busybear: more adapting to new memory system	2021-03-01 18:50:42 +00:00
Noah Boorstin	6e70ae8b3d	busybear: add 2nd dtim for bootram	2021-02-28 16:08:54 +00:00
Noah Boorstin	edd5e9106d	busybear: remove gpio, start adding 2nd ram	2021-02-28 06:02:40 +00:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
bbracker	9231646fb3	bus rw bugfix and peripherals testing	2021-02-12 00:02:45 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00