Ross Thompson
dcc00ef4b3
Renamed RW signals through the caches, bus interfaces, and IFU/LSU.
...
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
2022-09-23 11:46:53 -05:00
Ross Thompson
6a1b909a3f
Fixed up IFU ahb interface names and widths.
2022-09-19 10:54:22 -05:00
Ross Thompson
cc1ba84637
Found the ahb burst bug.
...
We had instruction fetches fixed HSIZE = 2 (4 bytes) for all requests. It should be HSIZE = 3 (8 bytes) for cache fetches and 4 for uncached reads. The reason this worked for non burst is the DDR4 memory controller returns the full double word even for 4 byte reads. In burst mode the second beat ending up pointing to the next 4 bytes rather than the next 8 bytes.
2022-09-17 20:30:01 -05:00
Ross Thompson
db56a326c9
renamed multimanager to multicontroller.
2022-09-14 14:03:37 -05:00
Ross Thompson
2ae62c2869
pipelining of fetch into evict AHB requests.
2022-09-13 17:51:55 -05:00
Ross Thompson
d12ceb46b0
Oups the ahbinterface.sv was accidentally named abhinterface.sv.
2022-09-08 13:21:37 -05:00
Ross Thompson
99e3f55637
Added logic to make burst optional.
2022-09-06 09:21:21 -05:00
Ross Thompson
20842b38b9
Names changes.
2022-09-05 20:49:35 -05:00
Ross Thompson
4e7a52a7a7
Cleaned up hacks to ram.
2022-09-04 14:52:40 -05:00
Ross Thompson
26bfaddb25
Disabled AHB burst mode, which discovered a bug.
...
Multimanger bug in how back to back requests were arbitrated.
2022-09-03 22:31:41 -05:00
Ross Thompson
4115087b30
Renamed state in buscachefsm to match AHB phases.
2022-09-02 17:17:40 -05:00
Ross Thompson
472fb5e888
Renamed states in busfsm to match AHB phases and book names.
2022-09-02 17:12:36 -05:00
Ross Thompson
15a2fbdd33
Possible fix for AHB trailing ~HREADY bug.
2022-09-02 16:58:35 -05:00
Ross Thompson
5b4e744972
marked possible improvement to ahb bus fsms.
2022-08-31 23:57:08 -05:00
Ross Thompson
5c8631fd16
Reduced busfsm to 3 states!
2022-08-31 16:11:59 -05:00
Ross Thompson
1cd7d8dbfe
Simplified.
2022-08-31 15:40:56 -05:00
Ross Thompson
ab4c75cbf5
More renaming.
2022-08-31 14:49:08 -05:00
Ross Thompson
6e85f850a4
Moved files.
...
Encapsulated ahbinterface.
2022-08-31 14:45:01 -05:00
Ross Thompson
d6d1c5d66d
Moved files around.
2022-08-31 14:08:06 -05:00
Ross Thompson
08d0c1cc83
Major cleanup of multimanager.
2022-08-31 12:40:25 -05:00
Ross Thompson
352f7443c2
Cleanup multimanager.
2022-08-31 12:04:44 -05:00
Ross Thompson
1e752c1268
cleanup of multimanager.
2022-08-31 11:38:06 -05:00
Ross Thompson
63a824cca1
More progress.
2022-08-30 15:27:19 -05:00
Ross Thompson
c8a5d61cbb
new cache bus fsm not working but lints.
...
Forgot a few files in the last commit.
2022-08-30 10:58:07 -05:00
Ross Thompson
4d7b905806
Part way through the updated bus fsm for direct AHB in lsu/ifu + multi-manager.
2022-08-29 13:01:24 -05:00
David Harris
0b918d6916
Separated busdp for cache from simpler logic for no cache
2022-08-25 17:54:04 -07:00
David Harris
5c1934208a
Simplified swbytemask
2022-08-25 17:32:16 -07:00
David Harris
b96942e84c
Removed delayed AHB signals from top level
2022-08-25 15:34:14 -07:00
David Harris
6222e15946
Extended HADDR to PA_BITS
2022-08-25 13:11:36 -07:00
David Harris
f782fe9367
Fixed brom name
2022-08-25 12:48:00 -07:00
David Harris
5b3c68fe74
ahblite cleanup
2022-08-25 12:44:25 -07:00
David Harris
cd02c894df
renamed BusBuffer to FetchBuffer
2022-08-25 10:44:39 -07:00
David Harris
5dc4fb757a
Continued busdp/ebu simplification
2022-08-25 10:20:02 -07:00
David Harris
89860588b8
Renamed AHB signals coming out of LSU to LSH_<AHBNAME>
2022-08-25 09:52:08 -07:00
David Harris
13d863a810
renamed GrantData to LSUGrant
2022-08-22 13:47:19 -07:00
Ross Thompson
f7e64fcd69
Fixed fstore2 in cache?
2022-08-01 22:04:44 -05:00
Ross Thompson
b8356c7449
Replaced swbytemask with swbytemaskword (1 liner). Credit to David Harris.
2022-08-01 21:12:25 -05:00
Ross Thompson
5d9dab6149
pulled swbbytemask out of subword write.
2022-08-01 20:48:45 -05:00
David Harris
381f3298d8
Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc
2022-07-08 09:09:02 +00:00
David Harris
d73645944f
APB CLINT passing regression
2022-07-05 15:51:35 +00:00
David Harris
4c48d71e4b
removed delay in ahblite
2022-07-05 04:59:28 +00:00
slmnemo
cadd62e49f
Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
2022-06-10 20:43:56 -07:00
slmnemo
dc11066ff2
Passed Regression: Seems to work perfectly fine
2022-06-09 18:21:13 -07:00
slmnemo
5a6eae214a
?
2022-06-09 17:50:47 -07:00
slmnemo
3e8d3bae88
Changes made on 9th Jun
2022-06-09 17:33:51 -07:00
slmnemo
81d373c7ab
Fixed error related to bus being unable to complete a line write after a memory read followed by an idle and cachewrite request.
2022-06-08 17:34:02 -07:00
slmnemo
11924bdd9b
Fixed error where MEMREAD would go into INSTRREAD even when no INSTRREAD was pending
2022-06-08 15:59:15 -07:00
slmnemo
e17ee3073e
Fixed ifu displaying LSU bus state in wave.do
2022-06-08 15:30:32 -07:00
slmnemo
315c2f0669
Working version: Fixed error where Word count would always increment even without AHB to bus ACK
2022-06-08 15:29:32 -07:00
slmnemo
054cf5f7b0
Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
2022-06-08 15:03:15 -07:00
