Ross Thompson
11f1613d59
Added additional fsm to ILA.
2022-01-12 14:17:16 -06:00
Ross Thompson
d8173745bb
Possible fix for the TrapM DTLBMiss suppression.
2022-01-12 14:17:16 -06:00
Ross Thompson
d14dffd010
Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
Ross Thompson
0f14d2ec88
Added advanced Vivado debug scripts.
2022-01-07 17:56:40 -06:00
Ross Thompson
6bd447d570
Patched the ILA's debug2.xdc constraint file to work with the wally memory design.
2022-01-06 15:18:18 -06:00
Ross Thompson
42623141cd
Updated fpga ILA constraints to match the new changes to the rtl.
2022-01-06 11:56:09 -06:00
Ross Thompson
5a2ae561a7
Updates to support fpga.
2022-01-05 18:07:23 -06:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
Ross Thompson
beb1988539
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
225cd5a114
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
a11597b6bd
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
6d2a4b8354
Oups missed files in the last commit.
2021-12-15 10:25:08 -06:00
Ross Thompson
21b13fc237
Reverted 23Mhz to 10Mhz. The flash card can't work at that speed.
...
added icache debugging signals.
2021-12-15 10:24:29 -06:00
Ross Thompson
af9f97454d
Cleaned up fpga synthesis script.
2021-12-13 18:26:54 -06:00
Ross Thompson
68745d40f2
Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language.
2021-12-12 17:21:44 -06:00
Ross Thompson
f2628494e3
Missed constraints file for xilinx ILA.
2021-12-12 15:06:29 -06:00
Ross Thompson
4dbd5d45ee
Added information on how to copy the linux image to flash card.
2021-12-07 13:16:38 -06:00
Ross Thompson
22721dd923
Added generate around the dtim preload.
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Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
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Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
Ross Thompson
955ddcfbe1
Fixed bug in the top level of fpga verilog.
2021-12-03 17:55:36 -06:00
Ross Thompson
5b4ff4526e
Fixed a bunch of fpga issues.
2021-12-03 17:47:54 -06:00
Ross Thompson
cbb5e4440f
Improved FPGA makefile and fixed timing constraints in clock converter.
2021-12-03 10:05:13 -06:00
Ross Thompson
96fb3acefd
Constraints for fpga are still wrong.
2021-12-02 14:23:21 -06:00
Ross Thompson
303324d370
Added tcl commands to build the implementation.
2021-12-02 10:17:30 -06:00
Ross Thompson
0d47749cb5
Separated timing constraints from ILA.
2021-12-01 18:15:04 -06:00
Ross Thompson
e94fb2aaec
Got fpga synthesis running from scripts.
2021-12-01 16:59:04 -06:00
Ross Thompson
5ea9ec0ae6
Created top level FPGA module which replicates the schematic of the initial fpga design.
2021-11-30 17:18:28 -06:00
Ross Thompson
d5f445e0fd
Added make clean to fpga IP generator.
2021-11-29 18:42:28 -06:00
Ross Thompson
a528a86607
Created Makefile to manage IP generation.
2021-11-29 18:33:58 -06:00
Ross Thompson
51807379a8
Added final IP generator script (proc_sys_reset).
2021-11-29 17:43:47 -06:00
Ross Thompson
8aa87958a9
Added ddr4 generator script.
2021-11-29 15:56:57 -06:00
Ross Thompson
da4ed957aa
Created tcl scripts to build 2 of the 4 xilinx IP.
2021-11-29 11:26:08 -06:00
Ross Thompson
9150133c7d
Fpga simualtion files.
2021-10-11 10:24:40 -05:00
