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138 Commits

Author SHA1 Message Date
Kevin Wan
3569998cb9 fixed tests.vh test lines 2023-04-28 07:47:59 -07:00
Kevin Wan
c0cbd0fd2a added tests for pmppriority module 2023-04-27 16:12:43 -07:00
Noah Limpert
26cb639f89 complete camline coverage on IFU and LSU 2023-04-27 14:26:10 -07:00
Noah Limpert
cf150a2ea9 Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00
Noah Limpert
73cca666bf Commiting changes to add coverage to ASID, Global, Megapage size checks. 2023-04-20 14:38:13 -07:00
David Harris
68295bd750
Update tests.vh 
Missing comma from merge
 2023-04-19 06:23:05 -07:00
David Harris
79dbfae4af
Merge branch 'main' into coverage4 2023-04-19 06:16:07 -07:00
David Harris
59d153ace0
Merge branch 'main' into main 2023-04-19 04:50:12 -07:00
David Harris
a13feb5d0b
Merge branch 'main' into main 2023-04-19 04:46:51 -07:00
Alec Vercruysse
3de03abd9d add D$ test case to trigger a FlushStage while SetDirtyWay=1 
This hits some conditional coverage in each cacheway.
A cache store hit happens at the same time as a StoreAmoMisalignedFault.
 2023-04-19 01:34:01 -07:00
Alec Vercruysse
cd9feb0260 Cover CacheWay edge case: CacheDataMem we=1 while ce=0. 
This test basically triggers an i$ miss during a d$ (hit) store
operation. It requires some tricky timing (e.g. a flushD right
before the relevant store). I use a script to generate the test.
 2023-04-19 01:34:01 -07:00
Liam
2a4bc01944 Update tests.vh 2023-04-18 23:15:47 -07:00
Kevin Wan
20a0803f46 Completely covers all PMPCFG_ARRAY_REGW cases 2023-04-18 21:50:48 -07:00
Kevin Wan
3ef81f4e6a PMPCFG_ARRAY_REGW cases 2023-04-18 18:43:50 -07:00
Kevin Thomas
385564fe4c Add PR#252 test file to coverage 2023-04-18 17:57:56 -05:00
Limnanthes Serafini
4ec28ef32d
Merge branch 'openhwgroup:main' into code_quality 2023-04-13 19:59:58 -07:00
Limnanthes Serafini
6fddc591b5 Finished up testbench reformatting 2023-04-13 19:18:26 -07:00
Limnanthes Serafini
99cd913d75 Further indents 2023-04-13 19:07:43 -07:00
Limnanthes Serafini
0862688168 testbench code visual improvements 2023-04-13 19:06:09 -07:00
David Harris
fe083e1edc
Merge pull request #243 from Noah-G-L/main 
Pull Request to add tlbKP.S - Fill in cache lines
 2023-04-13 18:13:04 -07:00
Limnanthes Serafini
51f6561476 A couple indents->spaces 2023-04-13 17:00:41 -07:00
Noah Limpert
419377a8f8 git did not seem to add tests.vh, trying again 2023-04-13 16:59:10 -07:00
Limnanthes Serafini
e33721fbe4 Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim 2023-04-13 16:54:16 -07:00
Limnanthes Serafini
ecce9b0ce1 Fix of InvalDelayed warning 2023-04-13 16:53:36 -07:00
Ross Thompson
f54868f19d
Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
David Harris
3b6e397172 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
David Harris
c5e3b5c68d Swapped in svadu mmu tests 2023-04-12 02:06:52 -07:00
Limnanthes Serafini
e0d27ff5a0
Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
James Stine
f5201da676 Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
Limnanthes Serafini
11a5b23bb8 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Kevin Box
f74bb8b38e Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
David Harris
a9b7bd101e Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
eroom1966
319a1b9161 fix break to simulation testbench 2023-04-06 14:45:41 +01:00
Ross Thompson
f2c26ff886
Merge pull request #206 from AlecVercruysse/coverage2 
i$ coverage improvements
 2023-04-05 17:29:35 -05:00
Alec Vercruysse
277f507e9a add ram1p1rwe for read-only cache ways (remove byte-enable) 
- increases coverage
 2023-04-05 11:48:18 -07:00
Limnanthes Serafini
7de772dcfe Merge remote-tracking branch 'upstream/main' into cachesim 2023-04-05 09:53:05 -07:00
David Harris
7373cbb3ff
Merge pull request #201 from ross144/main 
Improved d/i cache loggers
 2023-04-05 06:40:14 -07:00
Limnanthes Serafini
c42d798ff4 Commenting, attribution for sim, minor log changes 2023-04-05 02:43:02 -07:00
Limnanthes Serafini
6abd4ee1b7 Changed logging enables, debug mode in sim. 2023-04-04 23:49:35 -07:00
Limnanthes Serafini
8f3413f0d5 CacheSim edits, tests. I/D$ logging, Lim's version 2023-04-04 21:12:35 -07:00
Ross Thompson
5b188f239b Fixed the d cache logger. 2023-04-04 14:19:19 -05:00
Ross Thompson
b1a805d1f6 Improved d/i cache logger. 2023-04-04 13:38:32 -05:00
eroom1966
b9ef99530a add support for Sstc 2023-04-04 17:20:00 +01:00
David Harris
af8f1ab786 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-03 06:13:16 -07:00
James Stine
e3f3f14216 Update one bug in testfloat - still have to fix fpdiv but others should now all work 2023-04-02 18:16:23 -05:00
David Harris
800fdeb7ad Added SSTC support to imperas.ic and wallyTracer. Fixes many of the privileged tests 2023-03-31 10:54:03 -07:00
Sydney Riley
6c1f9de8c2 Manual merge in the coverage64gc 2023-03-29 15:25:27 -07:00
Sydney Riley
ede13491ef Starting IFU tests including c.fld compressed instruction 2023-03-29 15:15:47 -07:00
David Harris
4c41589329 Turned off hpm counters 2023-03-28 21:28:56 -07:00
David Harris
7132271a83 Started adding fpu fctrl tests 2023-03-28 21:13:25 -07:00