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26 Commits

Author SHA1 Message Date
Jarred Allen
602271ff7b rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
bbracker
98e93a63c0 maybe AHB works now 2021-03-18 17:47:00 -04:00
Jarred Allen
e69376c823 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-17 16:40:52 -04:00
Teo Ene
4fd0ecff69 Temporarily reverted my last few commits 2021-03-17 15:16:01 -05:00
Jarred Allen
36452749d7 Merge remote-tracking branch 'origin/main' into cache 2021-03-15 19:08:25 -04:00
Ross Thompson
4c8952de6a Converted branch predictor preloads to use system verilog rather than modelsim's load command. 2021-03-15 12:39:44 -05:00
Jarred Allen
926235b180 Merge upstream changes 2021-03-14 14:57:53 -04:00
Jarred Allen
deb13f34bb Get non-jump case working 2021-03-14 14:46:21 -04:00
Ross Thompson
845115302e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-10 15:37:02 -06:00
Ross Thompson
50a92247b3 Finally I think I have the function radix mapping across all applications correctly. I still need to clean up the code a bit so it is easier to understand. 2021-03-10 11:00:51 -06:00
Jarred Allen
ae9bcc174d Merge upstream changes 2021-03-09 21:20:34 -05:00
David Harris
17c0f9629a WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00
Jarred Allen
106718b196 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Ross Thompson
66e84f3a2c Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
David Harris
cf03afa880 Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
Teo Ene
c47872c2af Changed .do file back to run all 2021-02-25 09:58:54 -06:00
Ross Thompson
5df7e959f3 Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
2357f5513b Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
3551cc859b Data memory bus integration 2021-02-07 23:21:55 -05:00
David Harris
396cea1ea7 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00
David Harris
a357f2a0e7 Connected AHB bus to Uncore 2021-01-29 23:43:48 -05:00
David Harris
dc2443c55b Moving data memory to uncore 2021-01-29 15:37:51 -05:00
David Harris
824014c5c0 Repartitioned with Instruction Fetch Unit, Integer Execution Unit 2021-01-27 22:49:47 -05:00
David Harris
b88508ca11 Repartitioned datapath and controller into ieu 2021-01-27 06:40:26 -05:00
David Harris
fa18052348 Added test configurations 2021-01-25 11:28:43 -05:00