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c5e2443298
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874 Commits

Author SHA1 Message Date
Ross Thompson
c5e2443298 Replaced dcache generate ORing with or_rows. 2021-08-25 13:46:36 -05:00
Ross Thompson
e5336f4ee1 Rename of DCacheMem to cacheway. 
simplified dcache names.
 2021-08-25 13:33:15 -05:00
Ross Thompson
e9a1dc90f6 Removed generate around the dcache memories. 2021-08-25 13:27:26 -05:00
Ross Thompson
2ccf479354 Moved more logic inside the dcache memory. 2021-08-25 13:17:07 -05:00
Ross Thompson
35e57a7c61 partial dcache reorg. 2021-08-25 12:42:05 -05:00
David Harris
7d24ed3c51 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-08-25 06:47:20 -04:00
David Harris
3fa55a01f4 simplified or_rows generation and renamed oneHotDecoder to onehotdecoder 2021-08-25 06:46:41 -04:00
Ross Thompson
0cc47f3daf Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage. 2021-08-23 15:46:17 -05:00
Ross Thompson
c31b7b4dc5 Wally previously was overcounting retired instructions when they were flushed. 
InstrValidM was used to control when the counter was updated.  However this is
not suppress the counter when the instruction is flushed in the M stage.
 2021-08-23 12:24:03 -05:00
Ross Thompson
2825074114 Confirmed David's changes to the interrupt code. 
When a timer interrupt occurs it should be routed to the machine interrupt
pending MTIP even if MIDELEG[5] = 1 when the current privilege mode is
Machine.  This is true for all the interrupts. The interrupt should not be
masked even though it is delegated to a lower privilege.  Since the CPU
is currently in machine mode the interrupt must be taken if MIE.

Additionally added a new qemu script which pipes together all the parsing and
post processing scripts to produce the singular all.txt trace without the
massivie intermediate files.
 2021-08-22 21:36:31 -05:00
David Harris
4677b4bb38 possible interrupt code 2021-08-22 17:02:40 -04:00
Ross Thompson
65870877c3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-17 16:06:54 -05:00
Ross Thompson
91b51c698e Minor changes to dcache. 2021-08-17 15:22:10 -05:00
Katherine Parry
c8847b27e8 all conversions go through the execute stage result mux 2021-08-16 13:06:09 -04:00
Ross Thompson
a70d51f4c9 Modified the hptw's simulation error message so that synthesis does not attempt to include this statement. 2021-08-16 10:02:29 -05:00
Ross Thompson
36761d9155 Fixed syntax errors in some floating point modules. This came up in 
Xilinx synthesis.
 2021-08-15 16:48:49 -05:00
Ross Thompson
766c829d31 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-13 17:23:04 -05:00
Ross Thompson
55fda4de62 Switched ExceptionM to dcache to be just exceptions. 
Added test bench logic to hold forces until the W stage is unstalled.
 2021-08-13 15:53:50 -05:00
Katherine Parry
aedd71d570 move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Ross Thompson
6a6d5e9b15 Added documentation about how the dcache and ptw interact. 2021-08-12 18:05:36 -05:00
Ross Thompson
814fd80b0f Optimized subwordread to reduce critical path from 8 muxes to 5 muxes + 1 AND gate. 2021-08-12 13:36:33 -05:00
Ross Thompson
565c01709d Removed unused states from dcache fsm. 2021-08-11 17:06:09 -05:00
Ross Thompson
2be625d8b9 Modified invalid plic reads to return 0 rather than deadbeaf. 2021-08-11 16:56:22 -05:00
Ross Thompson
4b25fed6d8 Simplified Dcache by sharing the read data mux with the victim selection mux. 2021-08-11 16:55:55 -05:00
Ross Thompson
22f274c51e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-08-10 13:36:29 -05:00
Ross Thompson
67c1028862 Dcache and LSU clean up. 2021-08-10 13:36:21 -05:00
Katherine Parry
e00f181bcf LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Ross Thompson
cce0571925 Fixed another bug with the atomic instrucitons implemention in the dcache. 2021-08-08 22:50:31 -05:00
Ross Thompson
d3be04b7de Fixed another bug with AMO. If the CPU stalled as an AMO was finishing, the write to the 
cache's SRAM would occur.  Then in the next cycle the SRAM would be reread while stalled
providing the new update dated rather than the correct older value.
 2021-08-08 11:42:10 -05:00
Ross Thompson
fc7016eea6 Fixed the AMO dcache bug. The subword write needs to occur before the AMO logic. 
Fixed logic for trace update in the M and W stages.  The M stage should not update if there
is an instruction fault.
 2021-08-08 00:28:18 -05:00
Ross Thompson
c749d08542 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Ross Thompson
37ba6b19e5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-30 17:57:13 -05:00
Ross Thompson
7b9e53fbe5 Removed 1 cycle delay on store miss. 
Changed some logic to partially support atomics.
 2021-07-30 14:00:51 -05:00
Katherine Parry
d60e394ef9 all fpu units use the unpacking unit 2021-07-28 23:49:21 -04:00
Ross Thompson
915d8136e5 Fixed bug which caused stores to take an extra clock cycle. 2021-07-26 12:22:53 -05:00
Ross Thompson
79ebc53977 Fixed bug with the compressed immediate generation. Several formats should zero extend. 2021-07-26 11:55:31 -05:00
Ross Thompson
ef55b30e99 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
 2021-07-26 11:55:00 -05:00
Ross Thompson
60177b92a6 Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation. 2021-07-25 23:14:28 -05:00
Katherine Parry
30ac22edff fixed some fpu lint errors 2021-07-24 16:41:12 -04:00
Katherine Parry
6c4aa624a5 fpu cleanup 2021-07-24 15:00:56 -04:00
Katherine Parry
ef28679721 fpu cleanup 2021-07-24 14:59:57 -04:00
kipmacsaigoren
f3579032bd Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's 2021-07-23 11:57:58 -05:00
David Harris
5d2b30e332 Removed LEVELx states from HPTW 2021-07-23 08:11:15 -04:00
Ross Thompson
9939c66a1f Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 19:42:32 -05:00
Ross Thompson
3e916da36e Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle. 
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage.  Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM.  At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data.  When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
 2021-07-22 19:42:19 -05:00
David Harris
98660e0d19 Minor unpacking cleanup 2021-07-22 17:52:37 -04:00
Ross Thompson
551e3491af Moved the ReadDataW register into the datapath. 
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
 2021-07-22 14:52:03 -05:00
Ross Thompson
fbbfc799b9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 14:05:08 -05:00
Ross Thompson
9c90b4bdf7 Fixed bug with the itlb fault not dcache ptw ready state to ready state. 2021-07-22 14:04:56 -05:00
David Harris
c9890afb7f Move Z sign swapping out of unpacker 2021-07-22 14:32:38 -04:00