28 Commits

Author	SHA1	Message	Date
Ross Thompson	626bcd8608	Removed mark_debug from all source code.	2023-01-20 18:47:36 -06:00
David Harris	efe7e88258	csr cleanup	2023-01-13 22:12:06 -08:00
David Harris	25d8566694	csr comments	2023-01-13 20:49:34 -08:00
David Harris	b613722617	trap comments	2023-01-13 19:44:38 -08:00
David Harris	8c6ddcc15b	changed name to CORE-V-WALLY	2023-01-11 15:15:08 -08:00
David Harris	3ea4dd4898	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	739c2c8322	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	3b1fe78bdc	Removed unused StallW from CSRs	2022-12-23 00:21:36 -08:00
David Harris	0a7ed944a5	Revert to 98b824	2022-12-22 23:58:14 -08:00
David Harris	2d72bed1f4	Removed unused signals in FPU and CSR	2022-12-22 22:59:05 -08:00
David Harris	c7f3aae084	Only delegated bits of SIP are readable	2022-12-21 12:32:49 -08:00
David Harris	1aa3e65bae	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	e2e63ca9a8	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	8166fd772e	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	137b411bea	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	fb95767da0	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
Ross Thompson	19a8df9739	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
bbracker	69a0f6e00b	big interrupts refactor	2022-03-30 13:22:41 -07:00
Kip Macsai-Goren	56a0542405	made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes	2022-03-29 02:26:42 +00:00
Ross Thompson	61c714ebe6	I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.	2022-03-25 13:10:31 -05:00
bbracker	4b376e2834	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
Ross Thompson	849707f161	Switched csri IP_REGW to use assignements rather than always_comb as this is incompatible with forcing.	2022-03-22 22:04:06 -05:00
David Harris	d3034c4f01	Mostly removed N_SUPPORTED	2022-02-15 19:50:44 +00:00
Ross Thompson	e2343699d1	Factored out InstrValidNotFlushedM from each csr*.sv to csr.sv	2022-01-20 16:39:54 -06:00
Ross Thompson	a5f773220e	Updated CSR modules to prevent writting the registers when flushing. This only effects architecture writes not side effect writes.	2022-01-18 17:19:33 -06:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	c1d6550ccb	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00