Xavi/cvw
1
0
Fork 0
forked from Github_Repos/cvw
Code Issues Pull Requests Packages Projects Releases Wiki Activity
5,447 Commits 14 Branches 1 Tag 31 MiB
bb79b57cc1
Commit Graph

5447 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Kevin Kim
bb79b57cc1 alu bug fix 
- condmaskb piped in correctly instead of b
 2023-02-17 11:02:07 -08:00
Kip Macsai-Goren
02bc03af42 fixed makefile for 32 bit arch tests, restored original make for all others 2023-02-17 09:57:56 -08:00
Kip Macsai-Goren
70027a55b4 :Merge branch 'main' of github.com:kipmacsaigoren/cvw into main 2023-02-17 09:52:11 -08:00
Kip Macsai-Goren
b943470049 Modified arch64 tests to remove floating point and double tests from hanging make 2023-02-17 09:51:55 -08:00
Kevin Kim
a522ece3d3 Merge branch 'main' of https://github.com/kipmacsaigoren/cvw into main 2023-02-17 09:51:53 -08:00
Kevin Kim
ee3a520a1f alu looks at BSelect, added BSelect one hot signal 2023-02-17 09:51:49 -08:00
Kip Macsai-Goren
873dd718f1 merge with new changes to upstream 2023-02-17 09:36:58 -08:00
Kevin Kim
890c54bc0b added alu changes to previous commit 2023-02-17 08:22:13 -08:00
Kevin Kim
ec2421ead4 added BSelect Signal 
- BSelect [3:0] is a one hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction
 2023-02-17 08:21:55 -08:00
Kevin Kim
81cb00aaee comments 2023-02-17 07:53:14 -08:00
Kevin Kim
505f3bf42f comments 2023-02-17 07:52:54 -08:00
Kevin Kim
256d362e0d comment formatting 2023-02-17 07:51:28 -08:00
Kevin Kim
9ab8183e80 alu handles ALU select instead of funct3 2023-02-17 07:51:10 -08:00
Kevin Kim
9128ac5409 added BMU controll 2023-02-17 07:50:59 -08:00
Kevin Kim
25c0811d3d Added ALUSelect signal into datapath, ieu, controller 2023-02-17 07:50:45 -08:00
Ross Thompson
a6915a385a
Merge pull request #88 from stineje/main 
fix typo - remove extra p at end of script
 2023-02-16 15:53:39 -06:00
James Stine
8d94273a7a fix typo - remove extra p at end of script 2023-02-16 15:50:31 -06:00
Ross Thompson
a176325506
Merge pull request #87 from stineje/main 
Update bug in Makefile
 2023-02-16 15:25:43 -06:00
James Stine
c8307dffc1 Update bug in Makefile 2023-02-16 15:16:32 -06:00
Ross Thompson
3b7531b208
Merge pull request #86 from stineje/main 
Get rid of extra CR/LF in .synopsys_dc.setup file
 2023-02-16 15:13:48 -06:00
James Stine
fedbc1a43b Get rid of extra CR/LF in .synopsys_dc.setup file 2023-02-16 15:01:52 -06:00
David Harris
ba6eef1118
Merge pull request #85 from stineje/main 
Fix bugs in scripts for synthesis and tsmc28 psyn
 2023-02-16 11:54:21 -08:00
James Stine
004f8a970e Fix bugs in scripts for synthesis and tsmc28 psyn 2023-02-16 13:38:26 -06:00
David Harris
a65b82b533
Merge pull request #83 from stineje/main 
Update topo psyn stuff
 2023-02-16 06:34:59 -08:00
James Stine
64826a1ec9 Update topo psyn stuff 2023-02-16 08:07:17 -06:00
Kevin Kim
465aad372a added comments to zbc units 2023-02-15 17:42:32 -08:00
Kevin Kim
aad4d13603 zbc configurability and select mux 2023-02-15 17:39:37 -08:00
Kevin Kim
068ddc3e0d controller forwards funct7 
- started the bmu controll register
 2023-02-15 17:38:12 -08:00
Kevin Kim
6ac54a180e zbc and carry-less multiply work properly 2023-02-15 17:37:09 -08:00
Ross Thompson
4954f9df95
Merge pull request #82 from stineje/main 
Update if-then-else for ram items
 2023-02-15 18:16:44 -06:00
James Stine
744991bd5a Update if-then-else for ram items 2023-02-15 18:12:12 -06:00
David Harris
e0e8af4612
Merge pull request #80 from ross144/main 
Branch predictor acuracy fixes caused by last two weeks optimazations"
 2023-02-15 09:39:26 -08:00
Kevin Kim
cf8392cbd8 continued ZBC integration into ALU 2023-02-15 09:35:07 -08:00
Ross Thompson
69472b8145 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-15 11:29:39 -06:00
Ross Thompson
9c6ca3601a Merge branch 'main' of github.com:ross144/cvw 2023-02-15 11:28:50 -06:00
Ross Thompson
3aa26808fb
Merge pull request #79 from eroom1966/add-coverage 
add files to support coverage
 2023-02-15 11:18:25 -06:00
Kevin Kim
5426dd6184 added ALUResult Signal 2023-02-15 09:13:10 -08:00
eroom1966
0ac99d2233 add files to support coverage 2023-02-15 11:13:50 +00:00
Kevin Kim
9cec59ea2c controller passes funct7 from decode to execute 2023-02-14 16:06:10 -08:00
Kevin Kim
70f2dd701c git 2023-02-14 16:03:26 -08:00
Kevin Kim
9728e00dfd Merge branch 'tmp' into main 2023-02-14 13:12:57 -08:00
Kevin Kim
85c2ed8d34 removed unncessary stuff 2023-02-14 13:07:03 -08:00
Kevin Kim
8e371864e4 reverted back to I tests working 2023-02-14 13:06:31 -08:00
Ross Thompson
61d4040184
Merge pull request #77 from kevindkim723/patch-1 
fixed typo in LZC
 2023-02-14 13:20:55 -06:00
Kevin Kim
405bbcc6a4 added critical rsync command to python script and builds I-ext tests 
-rsync copies the stuff from riscof_work to work/riscv-arch-test
-
 2023-02-14 10:40:29 -08:00
Kevin Kim
fd46e0080c added ALU result select mux for B instructions 2023-02-13 17:38:00 -08:00
Kevin Kim
84ca2cab9c controller handles bclr 2023-02-13 16:57:05 -08:00
Ross Thompson
094b307724 Merge branch 'main' of github.com:ross144/cvw 2023-02-13 18:54:07 -06:00
Ross Thompson
9c9acc0055 Updated gshare (no speculation) to have better performance. 2023-02-13 18:52:52 -06:00
Kevin Kim
29abec2409 Shadd instructions pass tests 2023-02-13 16:36:17 -08:00