Kip Macsai-Goren
|
fbcb0c0bd8
|
Added missing ZFH macro to new configs
|
2022-04-06 07:13:51 +00:00 |
|
David Harris
|
7f462a6168
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-04-05 23:23:47 +00:00 |
|
David Harris
|
23da303ad3
|
Added bootmem source ccode
|
2022-04-05 23:22:53 +00:00 |
|
Ross Thompson
|
900939581e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-05 15:42:07 -05:00 |
|
Ross Thompson
|
5faa88acd5
|
Increazed fpga clock speed to 35Mhz.
linux boot is much faster.
|
2022-04-05 15:09:49 -05:00 |
|
David Harris
|
171b943254
|
Removed outdated sample testfloat calls
|
2022-04-04 17:23:39 +00:00 |
|
Katherine Parry
|
c3d07b2c46
|
generating all testfloat vectors
|
2022-04-04 17:17:12 +00:00 |
|
Ross Thompson
|
91e99f0d34
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-04 10:56:10 -05:00 |
|
Ross Thompson
|
077beb18dd
|
Constraint changes for 40Mhz wally.
|
2022-04-04 10:50:48 -05:00 |
|
Ross Thompson
|
b77201143f
|
Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.
|
2022-04-04 10:38:37 -05:00 |
|
Ross Thompson
|
400b5f7632
|
Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.
|
2022-04-04 09:57:26 -05:00 |
|
Ross Thompson
|
38160fe6ea
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-03 17:56:55 -05:00 |
|
Ross Thompson
|
3ebb7f1057
|
fpga simulation works again.
|
2022-04-03 17:31:07 -05:00 |
|
Ross Thompson
|
c4aadff487
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-03 17:30:47 -05:00 |
|
David Harris
|
fb95767da0
|
Fixed bug with CSRRS/CSRRC for MIP/SIP
|
2022-04-03 20:18:25 +00:00 |
|
Ross Thompson
|
3db60a1cc1
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-02 16:39:54 -05:00 |
|
Ross Thompson
|
2376d66ec2
|
Added more ILA signals.
|
2022-04-02 16:39:45 -05:00 |
|
Ross Thompson
|
35e8c6bb9c
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-02 16:35:59 -05:00 |
|
Kip Macsai-Goren
|
ba7f976f92
|
small bug fixes to 64 bit library
|
2022-04-02 19:17:34 +00:00 |
|
Kip Macsai-Goren
|
7412979b71
|
added unfinished tests to 32 bit library
|
2022-04-02 19:15:07 +00:00 |
|
Kip Macsai-Goren
|
c056e0dc5f
|
updated 32 bit tests to be in line with 64 bit test library
|
2022-04-02 19:14:12 +00:00 |
|
Kip Macsai-Goren
|
25984d1643
|
removed compressed instructions from privileged tests
|
2022-04-02 19:12:44 +00:00 |
|
Kip Macsai-Goren
|
37c755e6ce
|
added RV64IA config to have a config without compressed instructions
|
2022-04-02 18:24:08 +00:00 |
|
Ross Thompson
|
691f1a6b0d
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-01 17:18:25 -05:00 |
|
Ross Thompson
|
51dfa16f59
|
Updated the fpga test bench.
|
2022-04-01 17:14:47 -05:00 |
|
Ross Thompson
|
48c49802b2
|
Fixed linting issues.
|
2022-04-01 15:20:45 -05:00 |
|
Ross Thompson
|
301f20052b
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-04-01 12:50:34 -05:00 |
|
Ross Thompson
|
19a8df9739
|
Added wave config
added new signals to ILA.
|
2022-04-01 12:44:14 -05:00 |
|
David Harris
|
61e1758a69
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-04-01 16:49:18 +00:00 |
|
David Harris
|
c6960ede37
|
Changed Linux disassembly to -S to preserve source code lines
|
2022-04-01 16:49:13 +00:00 |
|
bbracker
|
9d26bfe71d
|
expand WALLY-PERIPH test to use SEIP on PLIC context 1
|
2022-03-31 18:02:06 -07:00 |
|
bbracker
|
e09079d8b4
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 17:54:43 -07:00 |
|
bbracker
|
55df8bc3f7
|
fix lingering overrun error bug
|
2022-03-31 17:54:32 -07:00 |
|
Ross Thompson
|
48c862d536
|
Added PLIC to ILA.
|
2022-03-31 16:44:49 -05:00 |
|
Ross Thompson
|
da93d14050
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 16:30:55 -05:00 |
|
Ross Thompson
|
b5cdf035fc
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 15:50:04 -05:00 |
|
Ross Thompson
|
ade4a4cd5e
|
Notes on what to change in ram.sv.
|
2022-03-31 15:48:15 -05:00 |
|
bbracker
|
bdb3417656
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 13:46:32 -07:00 |
|
bbracker
|
0f7e995055
|
simplify plic logic
|
2022-03-31 13:46:24 -07:00 |
|
David Harris
|
c7043e4d63
|
Added SystemVerilog flag to fma.do so that fma16 compiles properly
|
2022-03-31 17:00:38 +00:00 |
|
Ross Thompson
|
88c5cdc873
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 11:39:41 -05:00 |
|
Ross Thompson
|
bf9683f0d2
|
Forced to go back to hard coded preload.
|
2022-03-31 11:39:37 -05:00 |
|
Ross Thompson
|
54001222cf
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-31 11:38:55 -05:00 |
|
Ross Thompson
|
285fc6fd4d
|
Modified clint to support all byte write sizes.
|
2022-03-31 11:31:52 -05:00 |
|
David Harris
|
dd3af17b3f
|
Added synthesis script for fma16
|
2022-03-31 00:51:33 +00:00 |
|
David Harris
|
3457c6e512
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2022-03-30 23:06:36 +00:00 |
|
Ross Thompson
|
84a478c053
|
Updated constraints file.
|
2022-03-30 17:48:44 -05:00 |
|
Ross Thompson
|
471f204c48
|
Added bootrom.txt.
|
2022-03-30 17:29:48 -05:00 |
|
Ross Thompson
|
baf4d8875e
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2022-03-30 17:28:30 -05:00 |
|
bbracker
|
69a0f6e00b
|
big interrupts refactor
|
2022-03-30 13:22:41 -07:00 |
|