Ross Thompson
72363f5c66
Added the ability to exclude branch predictor.
2021-04-26 14:27:42 -05:00
Ross Thompson
8e5409af66
Icache integrated!
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Merge branch 'icache-almost-working' into main
2021-04-26 11:48:58 -05:00
Ross Thompson
6e803b724e
Merge branch 'tests' into icache-almost-working
2021-04-25 21:25:36 -05:00
bbracker
a3487a9e47
do script refactor
2021-04-24 09:32:09 -04:00
Noah Boorstin
3f0ead9d4e
yay buildroot passes a decent amount of tests now
...
gets through the first 15k instructions, that's good enough for now
also slight change to string parsing in busybear testbench
2021-04-19 03:26:08 -04:00
Noah Boorstin
6954e6df4c
buildroot: sim is now running!
...
yes it only gets through 5 instructions right now. Yes that's my fault.
2021-04-17 14:44:32 -04:00
Noah Boorstin
4f97e9e761
start to add buildroot testbench
...
This still uses testbench-busybear.sv
I think it might be time to finally rename nearly 'busybear' thing to 'linux'
2021-04-16 23:27:29 -04:00
Domenico Ottolia
92bb38fa8c
Add support for vectored interrupts
2021-04-15 19:13:42 -04:00
Thomas Fleming
303c2c4839
Implement support for superpages
2021-04-08 02:44:59 -04:00
bbracker
31c6b2d01f
Yee hoo first draft of PLIC plus self-checking tests
2021-04-04 06:40:53 -04:00
Ross Thompson
e1842c8da6
Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
2021-03-23 13:54:59 -05:00
Noah Boorstin
77dd0b4504
busybear: allow overwriting read values
2021-03-22 17:28:44 -04:00
bbracker
11d4a8ab34
first pass at PLIC interface
2021-03-22 10:14:21 -04:00
Shreya Sanghai
bbe0957df5
Merge branch 'gshare' into main
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Conflicts:
wally-pipelined/regression/wave.do
2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1
Switched to gshare from global history.
...
Fixed a few minor bugs.
2021-03-18 16:05:59 -05:00
Noah Boorstin
bc1a0c6ee7
change ifndef to generate/if
2021-03-18 12:50:19 -04:00
Noah Boorstin
ced2a32d21
busybear: update memory map, add GPIO
2021-03-18 12:17:35 -04:00
Noah Boorstin
e7fae21eb8
busybear: add COUNTERS define
2021-03-16 21:08:47 -04:00
Shreya Sanghai
36f0631203
added gshare and global history predictor
2021-03-16 17:03:01 -04:00
Shreya Sanghai
9eed875886
added global history branch predictor
2021-03-16 16:06:40 -04:00
Ross Thompson
4c8952de6a
Converted branch predictor preloads to use system verilog rather than modelsim's load command.
2021-03-15 12:39:44 -05:00
Thomas Fleming
1294235837
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Conflicts:
wally-pipelined/src/ebu/ahblite.sv
2021-03-11 00:15:58 -05:00
Ross Thompson
87ed6d510c
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062
Oups. I forgot to update other do files with the commands to preload the branch predictor memories.
2021-03-05 15:23:53 -06:00
Thomas Fleming
be6ee84d87
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-03-05 15:46:51 -05:00
Thomas Fleming
8c97143be6
Place tlb parameters into constant header file
2021-03-05 13:35:24 -05:00
Noah Boorstin
f48af209c4
busybear: make CSRs only weird for us
2021-03-05 00:46:32 +00:00
Noah Boorstin
26d4024b33
busybear: fix bootram range
2021-03-01 17:45:21 +00:00
Noah Boorstin
6e70ae8b3d
busybear: add 2nd dtim for bootram
2021-02-28 16:08:54 +00:00
Noah Boorstin
edd5e9106d
busybear: remove gpio, start adding 2nd ram
2021-02-28 06:02:40 +00:00
Noah Boorstin
4358f086be
update busybear testbench to conform to new structure
...
aaaaaaaaaaaaaaaaaahhhh so many changes
also the testbench now uses another internal signal,
which I don't like, but I can't think of a better option rn
2021-01-30 19:19:00 +00:00
Noah Boorstin
194d5b55ab
update busybear testbench to conform to new structure
2021-01-29 17:46:50 +00:00
Noah Boorstin
dabb026104
busybear: lie about MISA to match OVP's MISA
2021-01-29 00:58:56 -05:00
Noah Boorstin
6c567aab9a
Update busybear tests to conform to new directory structure
2021-01-25 20:37:18 -05:00
David Harris
fa18052348
Added test configurations
2021-01-25 11:28:43 -05:00
