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Author SHA1 Message Date
Ross Thompson
67f896637f
Merge pull request #149 from davidharrishmc/dev 
Fix issue 145 about PMP upper bits
 2023-03-22 11:13:43 -05:00
David Harris
c4c7f5378e Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
32c54db595 Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0 2023-03-22 04:41:57 -07:00
David Harris
dd517cdf00 Building infrastructure for coverage directed tests 2023-03-22 04:37:13 -07:00
David Harris
f33e3479cf Testbench improvements for coverage reporting and running Imperas suite to raise test coverage 2023-03-22 04:34:49 -07:00
David Harris
77fb1b57f4 Fix Issue 145 2023-03-22 04:33:14 -07:00
Kevin Kim
2e149f9a31 Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-21 11:20:05 -07:00
Ross Thompson
7e01f6d3e1
Merge pull request #146 from davidharrishmc/dev 
Many fixes
 2023-03-21 11:33:47 -05:00
David Harris
c91fa8e69e Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-21 06:58:29 -07:00
David Harris
3f47f4d665 Removed toggle coverage and generate recursive coverage report 2023-03-21 06:58:23 -07:00
David Harris
ba13add417 Added badinstr test file 2023-03-21 06:57:03 -07:00
David Harris
3fac9d98a2
Merge pull request #147 from stineje/main 
Add correction for regression on Sail due to bug in recent release.  …
 2023-03-21 06:44:46 -07:00
James Stine
e60b49952e Add correction for regression on Sail due to bug in recent release. This hash is known to work (verified by Stine/Thompson). May remove later if Sail ever gets fixed 2023-03-21 08:36:30 -05:00
David Harris
34457f68ec Commented out failing tests related to sip and sie 2023-03-21 05:51:43 -07:00
David Harris
376bbcc71d Renamed intdivrestoring to div 2023-03-21 05:51:02 -07:00
David Harris
0fd385e5de Renamed intdivrestoring to div 2023-03-20 16:22:06 -07:00
David Harris
67072b89e9
Update LICENSE to Soldered 2023-03-20 16:05:36 -07:00
Kevin Kim
73fbc21aab formatting 2023-03-20 14:25:05 -07:00
Kevin Kim
37b73ea42e more structural mux changes 2023-03-20 14:23:54 -07:00
Kevin Kim
7a6d1ab393 added bitmanip 64 tests to updated regression script 
+ alu structural mux changes
 2023-03-20 14:19:39 -07:00
Kevin Kim
728be29ce3 formatting 2023-03-20 13:09:49 -07:00
Kevin Kim
07a43e1935 Merge branch 'main' of https://github.com/openhwgroup/cvw into bit-manip 2023-03-20 13:06:10 -07:00
David Harris
0ecde4ab4f formatting cleanup 2023-03-20 12:45:10 -07:00
David Harris
6cc341a464
Merge pull request #144 from ross144/main 
Fixed bug in tool chain install script
 2023-03-20 10:40:44 -07:00
Ross Thompson
50a78fb674 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-20 11:52:18 -05:00
Ross Thompson
69d9bde358 Fixed bug in the tool chain install script. 2023-03-20 11:52:10 -05:00
Kevin Kim
9e5360e31f format + min/max structural mux 2023-03-20 09:37:57 -07:00
David Harris
471305bda0 Eliminate transitions to FLUSH and WRITEBACK in cachefsm for READ_ONLY_CACHE 2023-03-19 10:41:47 -07:00
David Harris
ab095de4b5 Ignore more log files left from ImperasDV 2023-03-19 10:26:53 -07:00
David Harris
8f3397df01 Renamed coverage-exclusions-rv64gc 2023-03-19 10:26:09 -07:00
David Harris
835381a122 Removed flq from LLEN=64 2023-03-19 10:25:04 -07:00
David Harris
563f243de3 Improved coverage reporting 2023-03-19 10:24:35 -07:00
David Harris
02e7e7d011 Added comments about PMP checker fixes when test cases will be ready to initialize PMP before entering user mode 2023-03-19 05:46:34 -07:00
David Harris
031cc6967a Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression. 2023-03-18 10:10:58 -07:00
David Harris
70e4c71f41 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-18 09:24:37 -07:00
David Harris
08ce265420 Replaced FenceM with InvalidateICacheM for event counting of fence.i 2023-03-18 09:24:31 -07:00
Mike Thompson
70d5b267ec
Merge pull request #140 from ross144/main 
Added notes on linux image generation
 2023-03-17 09:16:14 -04:00
Ross Thompson
e8d149df5e Merge branch 'main' of github.com:ross144/cvw into main 2023-03-17 00:48:04 -05:00
Ross Thompson
b5fa5bb47a Added notes on how to run QEMU to generate linux image. 2023-03-17 00:47:52 -05:00
Mike Thompson
112967142c
Merge pull request #139 from ross144/main 
Updates for book
 2023-03-14 15:44:59 -04:00
Ross Thompson
407b3c488d Book updates. 2023-03-14 13:09:50 -05:00
Ross Thompson
8d1a7154c2
Merge pull request #138 from eroom1966/main 
Fix MISA RO and UART addresses
 2023-03-13 23:32:56 -05:00
Ross Thompson
a27051b8a8 Updated NextAdr to NextSet. 2023-03-13 14:54:13 -05:00
Ross Thompson
cb019f9aed Updated CAdr to CacheSet. 2023-03-13 14:53:00 -05:00
Ross Thompson
c18a626abe More accurate c model gshare results. 2023-03-13 13:54:04 -05:00
Ross Thompson
ef2c5ce6a7 On our way to finish the C reference data collection. 2023-03-13 13:32:09 -05:00
Ross Thompson
77fe3c5546 Merge branch 'main' of github.com:ross144/cvw into main 2023-03-13 13:30:49 -05:00
Ross Thompson
c57e2a2140 Added reference data. 2023-03-13 13:30:43 -05:00
Ross Thompson
2d49c4582c Modified branch logger to indicate when the warmup period is done. 
The branch-predictor-simulator also changed to support this.
 2023-03-13 13:26:27 -05:00
eroom1966
0d260accb4 Fix MISA RO and UART addresses 
It appears on inspection that the MISA register is read only in Wally
In which case this has now also been set in the ImperasDV representation
Also the Addresss for the UART R/W privileges are corrected
 2023-03-13 11:07:19 +00:00