Ross Thompson
|
66e84f3a2c
|
Merge branch 'bp' into main
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
|
2021-03-04 13:35:46 -06:00 |
|
David Harris
|
2543c29839
|
Initial (untested) implementation of lr and sc
|
2021-03-01 00:09:45 -05:00 |
|
Ross Thompson
|
7592a0dacb
|
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
|
2021-02-26 20:12:27 -06:00 |
|
David Harris
|
cf03afa880
|
Eliminated flushing pipeline on CSR reads
|
2021-02-26 17:00:07 -05:00 |
|
David Harris
|
015b632eb1
|
Cleaned out unused signals
|
2021-02-26 09:17:36 -05:00 |
|
David Harris
|
a16fd95eed
|
Restored to working multiplier after Lab 2
|
2021-02-25 15:32:43 -05:00 |
|
David Harris
|
d00d42cf9a
|
Merged bus into main
|
2021-02-25 00:28:41 -05:00 |
|
David Harris
|
64536dbc34
|
Removed multiplier for lab 2
|
2021-02-17 16:06:16 -05:00 |
|
David Harris
|
cb0054b524
|
Multiply instructions working
|
2021-02-17 15:29:20 -05:00 |
|
David Harris
|
8dec69c2ce
|
Added MUL
|
2021-02-15 22:27:35 -05:00 |
|
David Harris
|
3551cc859b
|
Data memory bus integration
|
2021-02-07 23:21:55 -05:00 |
|
David Harris
|
aad1d3d7dd
|
Moved writeback pipeline registers from datapth into DMEM and CSR
|
2021-02-02 13:02:31 -05:00 |
|
David Harris
|
9d7e242596
|
Moved fpu to temporary location to fix compile and cleaned up interface formatting
|
2021-02-01 23:44:41 -05:00 |
|
David Harris
|
396cea1ea7
|
Reorganized src hierarchically
|
2021-01-30 11:50:37 -05:00 |
|