Kip Macsai-Goren
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8e72ace5ac
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fixed rv32ia to support clint and GPIO for priv tests
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2022-04-20 17:31:34 +00:00 |
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Shreya Sanghai
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a8b3cc8cf9
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added bpred size to wally config
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2022-04-18 04:21:03 +00:00 |
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David Harris
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b4902a6ff9
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First implementation of WFI timeout wait
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2022-04-17 17:20:35 +00:00 |
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Kip Macsai-Goren
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fbcb0c0bd8
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Added missing ZFH macro to new configs
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2022-04-06 07:13:51 +00:00 |
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Katherine Parry
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c3d07b2c46
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generating all testfloat vectors
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2022-04-04 17:17:12 +00:00 |
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Kip Macsai-Goren
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37c755e6ce
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added RV64IA config to have a config without compressed instructions
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2022-04-02 18:24:08 +00:00 |
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Ross Thompson
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51dfa16f59
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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Ross Thompson
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33b9b5423d
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reverted temporary change to configs.
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2022-03-22 22:31:34 -05:00 |
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Ross Thompson
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c233ef9768
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Reverted change to configuration which caused issue with lint.
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2022-03-22 21:44:08 -05:00 |
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Katherine Parry
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e3d01c875b
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FMA parameterized and FMA testbench reworked
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2022-03-19 19:39:03 +00:00 |
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Ross Thompson
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67ff8f27f4
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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bbracker
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a8e8cfb838
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switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv
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2022-03-01 03:11:43 +00:00 |
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bbracker
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202bd2f8f8
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change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
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2022-02-22 03:46:08 +00:00 |
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Ross Thompson
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0bd533473c
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New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
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2022-02-17 17:19:41 -06:00 |
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Ross Thompson
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4273775a2b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-08 14:22:19 -06:00 |
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David Harris
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510b47523a
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rv32e config update
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2022-02-08 17:59:50 +00:00 |
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Ross Thompson
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853a7bba18
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-02-08 11:36:30 -06:00 |
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Ross Thompson
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8a2ee22395
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Finished merge.
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2022-02-08 11:36:24 -06:00 |
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David Harris
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64e9f4c0d3
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Restored E tests to makefrag
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2022-02-08 16:41:11 +00:00 |
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David Harris
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c61cd55c5c
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Merged TIM and regular testbenches. RV32e now working and back in regression.
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2022-02-08 12:18:13 +00:00 |
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Ross Thompson
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d21be9d998
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Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
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2022-02-04 23:49:07 -06:00 |
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David Harris
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0f7b8017d1
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Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
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2022-02-05 05:35:51 +00:00 |
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David Harris
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72bc64ef28
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Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
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2022-02-05 04:16:18 +00:00 |
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David Harris
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fb041fe06a
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rv32e
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2022-02-04 01:56:30 +00:00 |
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David Harris
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ef5af9b5fd
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renamed configs
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2022-02-03 23:36:41 +00:00 |
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David Harris
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38bbe23d14
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More config file cleanup; 32ic tests broken
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2022-02-03 01:08:34 +00:00 |
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David Harris
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da8819d64b
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changed DMEM and IMEM configurations to support BUS/TIM/CACHE
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2022-02-03 00:41:09 +00:00 |
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David Harris
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68a6b4af3d
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Removed Busybear and Buildroot Configuration
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2022-02-02 20:32:22 +00:00 |
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David Harris
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4ba37d5cc0
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Config file & wally-riscv-arch-test cleanup
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2022-02-02 16:35:52 +00:00 |
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David Harris
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090533cfe9
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Replaced || and && with | and &
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2022-01-31 01:07:35 +00:00 |
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David Harris
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448acedd8b
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Set up rv32emc config
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2022-01-27 14:37:58 +00:00 |
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David Harris
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748375c82f
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Updated configs to fix GPIO address to match FU540
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2022-01-26 18:16:34 +00:00 |
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David Harris
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b63e53bbdb
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Defined rv32e and rv32emc configs
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2022-01-17 14:01:01 +00:00 |
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Ross Thompson
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3bec276862
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Added tim only test to regression-wally. Minor cleanup to ifu.
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2022-01-14 11:13:06 -06:00 |
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Ross Thompson
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a973681a90
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Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.
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2022-01-13 22:21:43 -06:00 |
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Ross Thompson
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aad28366d7
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Partial local dtim in lsu configuration.
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2022-01-13 17:50:31 -06:00 |
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Ross Thompson
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960af4b70f
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Set rv32ic to not use icache.
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2022-01-12 14:10:09 -06:00 |
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David Harris
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401a5b1779
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Removed unused coremark_bare
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2022-01-10 05:05:55 +00:00 |
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David Harris
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39d5570d2c
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Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.
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2022-01-10 05:04:13 +00:00 |
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Ross Thompson
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06168e67e4
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Switched block for line in caches.
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2022-01-04 22:08:18 -06:00 |
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David Harris
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b36ace221e
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Renamed wally-pipelined to pipelined
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2022-01-04 19:47:41 +00:00 |
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