27 Commits

Author	SHA1	Message	Date
David Harris	3ea4dd4898	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	654abcde61	Replaced MDUE with IntDivE in FDIVSQRT	2023-01-11 11:06:37 -08:00
David Harris	739c2c8322	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	8506f120e1	Remove unused signals	2023-01-07 05:46:22 -08:00
David Harris	44352ced64	Branch logic simplification and remove unused signals	2023-01-07 05:42:34 -08:00
David Harris	10af4e4353	ALU cleanup	2022-12-24 07:18:35 -08:00
David Harris	8f640f050f	IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI	2022-12-20 15:38:30 -08:00
Ross Thompson	35ad49502f	Implement FENCE.I as NOP when ZIFENCEI is not supported.	2022-12-20 17:34:11 -06:00
Ross Thompson	e774dd2db9	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
David Harris	5f637ef4a7	Use FPU divider for integer division when F is supported	2022-12-14 17:03:13 -08:00
David Harris	f08d5b23d5	Eliminated store after store stall when no cache; simplified divshiftcalc logic.	2022-09-21 13:02:34 -07:00
Ross Thompson	c6927d2ace	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
Madeleine Masser-Frye	fe31ee92e8	switched comparator to dc flip version	2022-06-21 20:30:33 +00:00
David Harris	1d8bc2dc1b	Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit	2022-06-02 09:37:59 -07:00
David Harris	faa15b1f8d	Cleaned up comments in controller	2022-06-02 15:48:33 +00:00
David Harris	e81e530f68	More signal cleanup	2022-05-12 15:39:44 +00:00
David Harris	1166c40059	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
David Harris	2cea3349ad	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
David Harris	a34cbdb7d0	Synthesis script cleanup, eliminated privileged instructiosn from controller when ZICSR_SUPPORTED = 0	2022-02-12 05:50:34 +00:00
David Harris	de5e80696d	Cleaned up synthesis warnings	2022-02-11 01:15:16 +00:00
David Harris	9b55848ffc	Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration	2022-02-06 01:22:40 +00:00
David Harris	da8819d64b	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	55b4423329	Added E extension, and downloaded riscv-dv and embench-iot to addins	2022-01-17 14:42:59 +00:00
David Harris	120fb7863f	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	1d8451c2cf	Capitalized LSU and IFU, changed MulDiv to MDU	2022-01-07 04:30:00 +00:00
David Harris	c1d6550ccb	Removed generate statements	2022-01-05 14:35:25 +00:00
David Harris	b36ace221e	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00