David Harris
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470bb6ed4d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-31 06:40:25 +00:00 |
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David Harris
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9f24b4c969
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Simplified performance counters
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2021-12-31 06:40:21 +00:00 |
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Ross Thompson
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b146c71b14
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-30 18:10:36 -06:00 |
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Ross Thompson
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5904bc68c7
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Patched up the linux-wave.do file.
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2021-12-30 17:53:43 -06:00 |
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David Harris
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42df98bc6d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-30 23:40:02 +00:00 |
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David Harris
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b96439dd73
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Fixes to counters; buildroot still broken
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2021-12-30 23:39:59 +00:00 |
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Ross Thompson
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6b59c03d1b
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No dcache now supported. Does not pass regression tests however.
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2021-12-30 15:26:32 -06:00 |
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David Harris
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2327f4b6bf
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Added names to generate blocks
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2021-12-30 20:55:48 +00:00 |
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David Harris
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d7653dedee
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Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion
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2021-12-30 17:22:18 +00:00 |
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Ross Thompson
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077bc35e10
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Updated lsu so it is possible to condictionally implement dcache or passthrough to ebu.
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2021-12-29 22:24:37 -06:00 |
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David Harris
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c54d81ab04
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Fixed generate statement name in csrm for buildroot regression
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2021-12-30 03:01:21 +00:00 |
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David Harris
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d8ba97cf71
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RV32ic tests running for simple machine with no privileged unit
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2021-12-30 02:25:46 +00:00 |
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David Harris
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98aaa970dd
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rv32i regression and linting
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2021-12-30 00:53:39 +00:00 |
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Ross Thompson
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050523487c
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Changed names of lsu address signals.
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2021-12-29 15:03:34 -06:00 |
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Ross Thompson
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b1116600fe
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Added more generates around virtual memory and csrs in the lsu.
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2021-12-29 14:48:09 -06:00 |
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David Harris
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52a38c5856
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Added performance counting to sumtest and added imperas32/64periph to testbench.
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2021-12-29 00:28:51 +00:00 |
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David Harris
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6e20d011d5
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Fixed imperas C tests
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2021-12-26 04:45:06 +00:00 |
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David Harris
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e6ed1372a7
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Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
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2021-12-26 04:36:53 +00:00 |
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David Harris
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48bb534658
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Started FIR test code and started incorporating Imperas tests
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2021-12-25 22:39:51 +00:00 |
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Ross Thompson
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50b307bc0e
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Looks like rdtime was accidentally replaced with rrame from a find and replace.
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2021-12-20 21:26:38 -06:00 |
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David Harris
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a25d541dcf
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Moved generate of conditional units to hart
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2021-12-19 17:03:57 -08:00 |
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David Harris
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3c3bfd055e
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Moved generate statements for optional units into wallypipelinedhart
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2021-12-19 16:53:41 -08:00 |
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Ross Thompson
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d9cc9afd49
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Changes to buildroot to support MemAdrM to IEUAdrM name changes.
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2021-12-19 18:24:40 -06:00 |
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David Harris
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aebd746e71
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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
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2021-12-15 12:10:45 -08:00 |
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David Harris
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865d5ce0b1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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David Harris
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2d24230093
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ALU and datapath cleanup
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2021-12-14 11:15:47 -08:00 |
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David Harris
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55f3979b67
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-13 07:57:49 -08:00 |
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David Harris
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2039752740
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Simplified ALU and source multiplexers pass tests
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2021-12-13 07:57:38 -08:00 |
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Kevin
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98420cb988
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dot stars conversions on the rest of the testbenches
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2021-12-12 17:53:26 -08:00 |
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Kevin
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1a82b50483
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edited one testbench, yet to run regression
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2021-12-10 20:26:20 -08:00 |
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bbracker
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f8cffca2b2
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-08 14:12:09 -08:00 |
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bbracker
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5feccaec68
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fix release of ReadDataM
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2021-12-08 14:11:43 -08:00 |
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Ross Thompson
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8b7cefab79
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-08 13:40:44 -06:00 |
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Ross Thompson
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9ddd065340
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Updated coremark testbench with the extra ports from FPGA merge.
Fixed coremark Makefile to create work directory.
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2021-12-08 13:40:32 -06:00 |
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bbracker
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979580b1e7
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fix checkpointing so that it can find the synchronized reset signal
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2021-12-07 13:12:06 -08:00 |
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Skylar Litz
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546f7fb4c2
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fix some interrupt timing bugs
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2021-12-03 12:32:38 -08:00 |
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Ross Thompson
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500e6ff430
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Fixed buildroot to work with the fpga's merge.
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2021-12-02 18:09:43 -06:00 |
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Ross Thompson
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b03ca464f1
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Mostly integrated FPGA flow into main branch. Not all tests passing yet.
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2021-12-02 18:00:32 -06:00 |
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Ross Thompson
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a871118116
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Merge branch 'main' into fpga
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2021-11-29 10:10:37 -06:00 |
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Ross Thompson
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5642918ead
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Merge branch 'main' into fpga
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2021-11-29 10:06:53 -06:00 |
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bbracker
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fed0bb08d6
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UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
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2021-11-25 11:01:59 -08:00 |
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bbracker
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cffb72042a
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activate STVAL for buildroot
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2021-11-21 10:40:28 -08:00 |
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David Harris
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82cfebfb83
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Coremark Cleanup, trying compile from addins
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2021-11-19 06:09:04 -08:00 |
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David Harris
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690410721d
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Cleaning up CoreMark benchmark
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2021-11-18 20:12:52 -08:00 |
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David Harris
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8e8b84f532
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vert "Simplifying riscv-coremark"
This reverts commit ce8232e396.
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2021-11-18 18:40:13 -08:00 |
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David Harris
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ce8232e396
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Simplifying riscv-coremark
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2021-11-18 17:15:40 -08:00 |
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David Harris
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402b473dbb
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CoreMark testing
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2021-11-18 16:14:25 -08:00 |
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David Harris
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0a281a06e0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-17 13:28:33 -08:00 |
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Skylar Litz
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6fde97b16c
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fixed interrupt timing bug
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2021-11-16 16:46:17 -08:00 |
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David Harris
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c610be25a7
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-11-16 12:30:55 -08:00 |
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