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Author	SHA1	Message	Date
Ross Thompson	6c8ac7851e	Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.	2022-07-19 22:42:25 -05:00
Katherine Parry	fb890d621d	moved ctrl signal registers into fctrl, also a lot of code cleaning	2022-07-20 02:27:39 +00:00
cturek	d7e90a7086	divsqrt working for floating point	2022-07-20 02:04:20 +00:00
cturek	f75d1c2eef	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-20 02:00:50 +00:00
cturek	8e66b81821	New radix-2 algorithm implemented and working	2022-07-20 02:00:43 +00:00
David Harris	9d125addfa	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-20 01:49:36 +00:00
David Harris	4c740e1494	Reordered embench Makefile to run size tests first	2022-07-20 01:49:33 +00:00
cturek	db39a05abc	small changes	2022-07-20 01:36:25 +00:00
Katherine Parry	531829f7c8	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-19 23:44:41 +00:00
Katherine Parry	afcddf7035	oprimized zeros and replaced complex ?: with always_comb	2022-07-19 23:44:37 +00:00
Daniel Torres	7632ce9ee9	embench no longer launches run automatiacally, need to use make run	2022-07-19 15:16:12 -07:00
Daniel Torres	d33d0d22bd	commented out embench 2.0 tests	2022-07-19 13:36:18 -07:00
Daniel Torres	2c2c8d4d9b	made changes to makefile, now builds fastest version (RV64im) by default. Also removed redundent CFLAG funroll-all-loops (was duplicated)	2022-07-19 13:17:02 -07:00
slmnemo	77f7b179ee	fixed GPIO test by adding a new function to clear PLIC interrupts	2022-07-19 08:59:16 -07:00
Ross Thompson	ffda64587c	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
David Harris	38fac8e05c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-19 02:58:13 +00:00
David Harris	8caab918ec	Removed duplicate -march from CoreMark makefile	2022-07-19 02:58:07 +00:00
Katherine Parry	4c2afbbc4f	moved Se into execute stage	2022-07-19 01:10:10 +00:00
Katherine Parry	a590728350	reworked fmashiftcalc to match book	2022-07-19 00:04:24 +00:00
David Harris	6ec2a5db4a	Coremark cleanup	2022-07-18 16:48:13 -07:00
David Harris	59eb11b73a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 23:11:12 +00:00
David Harris	ab08826b6a	Cleaned up Coremark makefile	2022-07-18 23:10:22 +00:00
Katherine Parry	86f0327f79	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 20:49:01 +00:00
Katherine Parry	e599f82b29	moved Ss to execute stage	2022-07-18 20:48:56 +00:00
Daniel Torres	a190bc4471	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-18 13:30:50 -07:00
Daniel Torres	877d0b7364	added additional changes to coremark to support rv32	2022-07-18 13:30:35 -07:00
Daniel Torres	c65aa54a1e	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-18 12:13:48 -07:00
Daniel Torres	3f5a5e1093	added the sail change to spike to let it all run normally	2022-07-18 12:13:15 -07:00
Katherine Parry	921debf930	removed underflow from inexactct calculation	2022-07-18 17:51:18 +00:00
Katherine Parry	ea7b32a50b	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 17:31:29 +00:00
Katherine Parry	5bb1478859	renamed signals in ocde to match book	2022-07-18 17:31:17 +00:00
David Harris	f4c1c867d0	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-18 10:19:20 +00:00
Ross Thompson	a88543275f	Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.	2022-07-17 21:05:31 -05:00
Ross Thompson	3670c47141	Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.	2022-07-17 16:20:04 -05:00
James Stine	2753699fb2	Add back extractSummary mkdir plots	2022-07-17 13:00:44 -05:00
David Harris	7c744f0053	Rewrote convert shift calculation with always for ease of reading	2022-07-17 16:40:58 +00:00
James Stine	3815f19763	Add import os in extractSummary.py	2022-07-17 11:06:30 -05:00
David Harris	7f8ee1e5f4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-17 01:40:03 +00:00
David Harris	2a965cf634	Don't delete hdl directory at end of run	2022-07-17 01:39:57 +00:00
David Harris	6e1d4ec4ed	restored intPending logic to be sticky for PLIC	2022-07-16 17:43:31 -07:00
Katherine Parry	a4cd157f00	forgot some files	2022-07-15 21:42:45 +00:00
Katherine Parry	e498d87c5c	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-15 20:17:08 +00:00
Katherine Parry	e251022269	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
cturek	ec9536f983	Square root radix 2 working, does not work with division	2022-07-14 22:52:09 +00:00
cturek	9f18f6a203	Square root	2022-07-14 21:19:45 +00:00
cturek	38bbd19abf	Six tests passing and a bunch of sizizing issues fixed	2022-07-14 19:38:27 +00:00
Katherine Parry	a0e9e93d4f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-14 18:16:13 +00:00
Katherine Parry	b069cfbec2	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
cturek	f49c2a969f	S and SM are updating but are not correct yet	2022-07-14 00:39:30 +00:00
Katherine Parry	8506d2be4c	fixed uncommented line in makefile	2022-07-14 00:01:07 +00:00