David Harris
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8b44037f58
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Parameterized fmalza
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2022-08-01 16:18:02 -07:00 |
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David Harris
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6e78b46761
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Completed LZA simplificaiton
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2022-08-01 16:13:16 -07:00 |
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David Harris
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76021769a7
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lza cleanup
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2022-08-01 16:01:02 -07:00 |
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David Harris
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47d204f4a2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-01 15:47:58 -07:00 |
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David Harris
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c8d4f3a542
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lza cleanup
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2022-08-01 15:47:03 -07:00 |
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David Harris
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c531df9c4e
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lza cleanup
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2022-08-01 15:43:48 -07:00 |
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David Harris
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5468a90cf3
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lza cleanup
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2022-08-01 15:40:12 -07:00 |
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David Harris
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4953ccf273
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lza cleanup
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2022-08-01 15:37:09 -07:00 |
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Katherine Parry
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66eca28ccd
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regression passes fpu tests
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2022-08-01 19:56:25 +00:00 |
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Katherine Parry
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9672f5451a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-01 19:55:50 +00:00 |
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David Harris
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31215277ee
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more lza cleanup
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2022-08-01 12:34:00 -07:00 |
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David Harris
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48500c642c
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LZA cleanup
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2022-08-01 12:30:42 -07:00 |
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David Harris
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87e6402af6
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LZA refactoring switched to Pp1, Gm1, Km1
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2022-08-01 12:20:23 -07:00 |
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David Harris
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5012b96120
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LZA refactoring
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2022-08-01 11:36:21 -07:00 |
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Katherine Parry
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75f39e0c5b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-08-01 18:35:07 +00:00 |
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David Harris
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231f52c1fd
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fmalza edits to match textbook
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2022-08-01 18:23:39 +00:00 |
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David Harris
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e3b970d3ff
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Partitioned fma into separate files
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2022-08-01 18:07:38 +00:00 |
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Katherine Parry
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de03954946
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re-added FStore2 in Cache
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2022-07-29 22:54:49 +00:00 |
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David Harris
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d2de84a456
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Added parity and stop bit tests to UART
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2022-07-28 04:35:51 +00:00 |
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Ross Thompson
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70032bf8f4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-23 08:41:59 -05:00 |
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Ross Thompson
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5cd6c8069d
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signal name cleanup.
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2022-07-22 23:36:27 -05:00 |
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Ross Thompson
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7d026e02f2
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cache cleanup after removing replay on cpubusy.
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2022-07-22 23:30:25 -05:00 |
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Ross Thompson
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706bc819e1
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cache fsm cleanup after removal of replay.
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2022-07-22 23:25:09 -05:00 |
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Ross Thompson
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0f586c9ed3
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Possible improvement to cache which removes the cpu_busy states.
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2022-07-22 23:20:37 -05:00 |
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Katherine Parry
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bd336f18b3
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merged radix-2 sqrt into divider - doesnt work yet
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2022-07-23 00:41:18 +00:00 |
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slmnemo
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5b71ceac5c
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-22 17:13:38 -07:00 |
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slmnemo
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0bfc3fda1b
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Fixed UART FIFO bugs and added FIFO tests
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2022-07-22 17:13:19 -07:00 |
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Katherine Parry
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ee7932c804
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divider sizes reworked to match book
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2022-07-22 22:02:04 +00:00 |
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David Harris
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07c946bb04
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Reset MSR on read
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2022-07-22 04:29:27 +00:00 |
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slmnemo
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bfa500234d
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Fixed UART bug related to parity and MSR/LSR
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2022-07-21 20:35:46 -07:00 |
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Katherine Parry
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270216dd02
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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Katherine Parry
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67c99d3d1a
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added input enables and improved forwarding
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2022-07-21 01:20:06 +00:00 |
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Katherine Parry
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e8c9830b88
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turn off 2 word store durring non-fp instructions
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2022-07-20 21:57:23 +00:00 |
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Ross Thompson
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9868e685a4
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Minor cleanup of cache.
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2022-07-19 23:04:23 -05:00 |
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Ross Thompson
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6c8ac7851e
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Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
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2022-07-19 22:42:25 -05:00 |
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Katherine Parry
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fb890d621d
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moved ctrl signal registers into fctrl, also a lot of code cleaning
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2022-07-20 02:27:39 +00:00 |
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cturek
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db39a05abc
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small changes
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2022-07-20 01:36:25 +00:00 |
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Katherine Parry
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afcddf7035
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oprimized zeros and replaced complex ?: with always_comb
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2022-07-19 23:44:37 +00:00 |
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Ross Thompson
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ffda64587c
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Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
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2022-07-18 23:37:18 -05:00 |
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Katherine Parry
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4c2afbbc4f
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moved Se into execute stage
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2022-07-19 01:10:10 +00:00 |
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Katherine Parry
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a590728350
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reworked fmashiftcalc to match book
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2022-07-19 00:04:24 +00:00 |
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David Harris
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59eb11b73a
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-18 23:11:12 +00:00 |
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Katherine Parry
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e599f82b29
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moved Ss to execute stage
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2022-07-18 20:48:56 +00:00 |
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Katherine Parry
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921debf930
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Katherine Parry
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ea7b32a50b
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-18 17:31:29 +00:00 |
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Katherine Parry
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5bb1478859
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renamed signals in ocde to match book
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2022-07-18 17:31:17 +00:00 |
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Ross Thompson
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a88543275f
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Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
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2022-07-17 21:05:31 -05:00 |
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Ross Thompson
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3670c47141
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Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
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2022-07-17 16:20:04 -05:00 |
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David Harris
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7c744f0053
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Rewrote convert shift calculation with always for ease of reading
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2022-07-17 16:40:58 +00:00 |
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David Harris
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6e1d4ec4ed
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restored intPending logic to be sticky for PLIC
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2022-07-16 17:43:31 -07:00 |
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