bbracker
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13cf7c0934
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linux testbench now ignores HWRITE glitches caused by flush glitches
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2021-06-25 09:28:52 -04:00 |
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bbracker
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53d545cdfe
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regression can overcome the fact that buildroots UART prints stuff
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2021-06-24 02:00:01 -04:00 |
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bbracker
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cee468b21a
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whoops meant to remove notifications from busybear, not buildroot
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2021-06-24 01:54:46 -04:00 |
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bbracker
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be962cb1ff
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overhauled linux testbench and spoofed MTTIME interrupt
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2021-06-24 01:42:35 -04:00 |
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David Harris
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a514554eeb
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Reduced complexity of pmpadrdec
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2021-06-23 03:03:52 -04:00 |
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bbracker
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9b27cd6fb7
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added slack notifier for long sims
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2021-06-22 08:31:41 -04:00 |
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bbracker
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2643130c41
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read from MSTATUS workaround because QEMU has incorrect MSTATUS
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2021-06-20 10:11:39 -04:00 |
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bbracker
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dc26f2a6d0
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whoops wavedo typo
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2021-06-20 05:36:54 -04:00 |
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bbracker
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c77aabdc6f
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make buildroot ignore SSTATUS because QEMU did not originally log it
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2021-06-20 05:31:24 -04:00 |
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bbracker
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086f031b84
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remove lingering busybear stuff from buildroot do files
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2021-06-20 00:50:53 -04:00 |
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bbracker
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d62d9a7aac
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make buildroot waves only turn on after a user-specified point
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2021-06-20 00:39:30 -04:00 |
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David Harris
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33312caeb1
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Restored wally-busybear testbench now that graphical sim is working
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2021-06-18 12:36:25 -04:00 |
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bbracker
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4f50dd575d
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buildroot added to regression because it passes regression
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2021-06-18 09:49:30 -04:00 |
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David Harris
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336936cc39
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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5b96f7fbd7
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making linux waveforms more useful
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2021-06-17 08:37:37 -04:00 |
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bbracker
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28c6d60150
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temporarily removing buildroot from regression until it is regenerated
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2021-06-07 13:20:50 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Ross Thompson
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41a1e6112a
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-06-04 15:16:39 -05:00 |
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Ross Thompson
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7406e33b61
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Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
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2021-06-04 15:14:05 -05:00 |
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Ross Thompson
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191f7e61fd
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Moved I-Cache offset selection mux to icache.sv (top level).
When we switch to set associative this is will be more efficient.
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2021-06-04 13:49:33 -05:00 |
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Katherine Parry
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fc65aedbd6
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Double-precision FMA instructions
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2021-06-04 14:00:11 -04:00 |
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Ross Thompson
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fdef8df76b
|
Reorganized the icache names.
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2021-06-04 12:53:42 -05:00 |
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David Harris
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0674f5506e
|
moved shared constants to a shared directory
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2021-06-03 22:41:30 -04:00 |
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bbracker
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4e765ee1c5
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expanded GPIO testing and caught small GPIO bug
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2021-06-03 10:03:09 -04:00 |
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bbracker
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2c77a13c08
|
fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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bbracker
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39ae743543
|
turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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bbracker
|
846553ac7d
|
improved PLIC test organization
|
2021-05-21 15:13:02 -04:00 |
|
Katherine Parry
|
06af239e6c
|
FMV.D.X imperas test passes
|
2021-05-20 22:17:59 -04:00 |
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bbracker
|
1d3db5ead5
|
small bit of busybear debug progress
|
2021-05-19 20:18:00 -04:00 |
|
James E. Stine
|
304e70d3ae
|
Update rv64icfd batch script
|
2021-05-18 16:01:53 -05:00 |
|
David Harris
|
5da159d17e
|
Removed rv64wally
|
2021-05-18 14:08:46 -04:00 |
|
David Harris
|
4d264c6f61
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/regression/vish_stacktrace.vstf
|
2021-05-18 14:01:19 -04:00 |
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bbracker
|
f00eb22700
|
fixed busybear floating point NOP-out feature; restored regression to check 100000 instructions
|
2021-05-17 19:25:54 -04:00 |
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bbracker
|
e4c90f503a
|
regression modified to timeout after 10 min \n took Harris\' suggestion for avoiding using ahbliteState package in busybear testbench
|
2021-05-17 18:44:47 -04:00 |
|
David Harris
|
9901f54b15
|
Deleted vish_stacktrace
|
2021-05-17 18:39:01 -04:00 |
|
Elizabeth Hedenberg
|
b818ce608a
|
commit ehedenberg coremark
|
2021-05-17 18:02:35 -04:00 |
|
James E. Stine
|
3d3e3434f6
|
Cleanup of regression
|
2021-05-17 16:58:15 -05:00 |
|
James E. Stine
|
865b3ee219
|
Updates on Divide - pushed in working version of DIV64U for Divide and REmainder. Will do 32-bit version tomorrow as well as Signed version
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2021-05-17 16:48:51 -05:00 |
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Thomas Fleming
|
6aa04af38d
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-14 07:40:08 -04:00 |
|
Thomas Fleming
|
ea4e76938e
|
Remove busy-mmu and fix missing signal
|
2021-05-14 07:14:20 -04:00 |
|
Jarred Allen
|
041149eaf7
|
Minor fixes in regression
|
2021-05-09 13:57:09 -04:00 |
|
Jarred Allen
|
c7f400262c
|
Fix bug in regression script
|
2021-05-06 12:56:57 -04:00 |
|
Jarred Allen
|
be029ba02c
|
Clean up regression script and document it
|
2021-05-04 18:58:59 -04:00 |
|
Thomas Fleming
|
ad40464557
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-03 23:15:39 -04:00 |
|
Elizabeth Hedenberg
|
2d1d929485
|
coremark print statment
|
2021-05-03 19:35:08 -04:00 |
|
Elizabeth Hedenberg
|
463ba1a2be
|
coremark directory changes
|
2021-05-03 19:35:06 -04:00 |
|
Ross Thompson
|
82b4d42f32
|
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
|
2021-05-03 16:56:00 -05:00 |
|
Ross Thompson
|
7f38056879
|
fixed subtle typo in icache fsm. Was messing up hit spill hit.
I believe the mibench qsort benchmark runs after this icache fix.
|
2021-05-03 16:55:36 -05:00 |
|
Thomas Fleming
|
ba1afec621
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-05-03 17:38:13 -04:00 |
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