Ross Thompson
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21526957cf
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Updated fpga test bench.
Solved read delay cache bug. Introduced during cache optimizations.
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2022-08-21 15:59:54 -05:00 |
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Ross Thompson
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96d6218078
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Possible reduction of ignorerequest.
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2022-08-19 18:07:44 -05:00 |
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Ross Thompson
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5301444a61
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Changed signal names.
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2022-08-17 16:12:04 -05:00 |
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Ross Thompson
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970a90dd72
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Better name for LSUBusWriteCrit. Changed to SelLSUBusWord.
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2022-08-17 16:09:20 -05:00 |
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Ross Thompson
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f7e64fcd69
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Fixed fstore2 in cache?
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2022-08-01 22:04:44 -05:00 |
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Ross Thompson
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171cf7413b
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Replaced LOGWPL with LOGBWPL (Bus words per line) and LOGCWPL (cache words per line). Replaced with wordlen/8 bytemask.
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2022-08-01 21:08:14 -05:00 |
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Ross Thompson
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5cd6c8069d
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signal name cleanup.
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2022-07-22 23:36:27 -05:00 |
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Katherine Parry
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ca4fe08fd9
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renamed FLoad2 to FStore2
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2022-07-09 00:26:45 +00:00 |
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Katherine Parry
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cd53ae67d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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Madeleine Masser-Frye
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cb33d2289b
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fixed width mismatch for rv64 ieuadrM and readdatawordM
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2022-07-06 22:39:35 +00:00 |
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Katherine Parry
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6baded9121
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added rv32 double precision stores - untested
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2022-06-28 21:33:31 +00:00 |
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slmnemo
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054cf5f7b0
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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
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2022-06-08 15:03:15 -07:00 |
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slmnemo
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284e0395a0
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
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2d76953d42
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
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slmnemo
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73e0c1c07f
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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David Harris
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c7ec9282fe
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Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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slmnemo
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847c7930c4
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added LSUBurstDone signal to signal when a burst has finished
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2022-05-26 16:29:13 -07:00 |
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slmnemo
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08430a1e85
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added burst size signals to the IFU, EBU, LSU, and busdp
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2022-05-25 18:02:50 -07:00 |
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slmnemo
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8c8a7daec2
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Fixed grammar on two comments in bpred.sv
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2022-05-16 22:41:18 +00:00 |
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David Harris
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ce24c080d5
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More unused signal cleanup
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2022-05-12 15:26:08 +00:00 |
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David Harris
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5670f77de2
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More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
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David Harris
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1a7599ce94
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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Kip Macsai-Goren
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bd87af478a
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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David Harris
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eaa0d44980
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Fixed WFI decoding in IFU
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2022-04-18 19:02:08 +00:00 |
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Shreya Sanghai
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6f0085201b
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replaced k with bpred size
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2022-04-18 04:21:03 +00:00 |
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David Harris
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0932d4df46
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Added WFI support to IFU to keep it in the pipeline
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2022-04-14 17:26:17 +00:00 |
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Ross Thompson
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396f697d2f
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Hacky fix to prevent ITLBMissF and TrapM bug.
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2022-04-12 17:56:23 -05:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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e4f4e1bd43
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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David Harris
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c4f2c6b110
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fpu compare simplification, minor cleanup
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2022-03-29 17:11:28 +00:00 |
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Ross Thompson
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fe896bff8e
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Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
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2022-03-24 23:47:28 -05:00 |
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Ross Thompson
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ee4b38dce3
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dtim writes are supressed on non cacheable operation.
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2022-03-12 00:46:11 -06:00 |
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Ross Thompson
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67ff8f27f4
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Can now support the following memory and bus configurations.
1. dtim/irom only
2. bus only
3. dtim/irom + bus
4. caches + bus
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2022-03-11 15:18:56 -06:00 |
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Ross Thompson
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9dce2a0679
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Towards allowing dtim + bus.
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2022-03-11 14:58:21 -06:00 |
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Ross Thompson
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b7a680ec2a
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Moved subcachelineread inside the cache. There is some ugliness to still resolve.
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2022-03-11 12:44:04 -06:00 |
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Ross Thompson
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a18f06c20b
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Moved subcacheline read inside the cache.
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2022-03-11 11:03:36 -06:00 |
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Ross Thompson
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52cc852600
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removed unused parameter.
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2022-03-11 10:43:54 -06:00 |
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Ross Thompson
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6d914def08
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Name cleanup.
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2022-03-10 18:44:50 -06:00 |
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Ross Thompson
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63b1ea88c9
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Signal name cleanup.
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2022-03-10 18:26:58 -06:00 |
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Ross Thompson
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396c97fc36
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Byte write enables are passing all configs now.
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2022-03-10 17:26:32 -06:00 |
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Ross Thompson
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7a129c75cd
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Added byte write enables to cache SRAMs.
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2022-03-10 15:48:31 -06:00 |
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David Harris
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bc2b757952
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bit write update
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2022-03-09 19:09:20 +00:00 |
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David Harris
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27f09ffb33
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Refactored SRAM bit write enable
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2022-03-09 17:49:28 +00:00 |
|
Ross Thompson
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3ec32d7ce8
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Removed unused signal.
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2022-03-08 16:58:26 -06:00 |
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Ross Thompson
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d78ba777a4
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Added parameter to spillsupport.
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2022-03-08 16:38:48 -06:00 |
|
Ross Thompson
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7b96b3f73c
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Moved cacheable signal into cache.
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2022-03-08 16:34:02 -06:00 |
|
Ross Thompson
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730fdb029a
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Fixed bug with DAPageFault being wrong when HPTW writes not supported.
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2022-02-23 10:54:34 -06:00 |
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Ross Thompson
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6f53f7943f
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More spillsupport more structual.
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2022-02-23 10:27:14 -06:00 |
|
Ross Thompson
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19ec874641
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Fixed bug with spill support and Instruction DA Page Faults.
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2022-02-23 10:16:12 -06:00 |
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Ross Thompson
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15f6871a8d
|
Added generates to pcnextf muxes for privileged and caches.
|
2022-02-22 22:45:00 -06:00 |
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