Ross Thompson
132016f131
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-09 12:19:44 -05:00
David Harris
4a2f641348
Waived coverage on BTB memory with byte write enables tied high
2023-04-07 21:56:49 -07:00
Ross Thompson
fe922c8fac
Fixed syntax error.
2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1
Added note about strange vivado behavior not inferring block ram.
2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997
Similifed the no byte write enabled version of the sram model.
2023-04-06 14:18:41 -05:00
Alec Vercruysse
2a3d9f8c89
Update ram1p1rwe (ce & we) coverage exlusion explanation
2023-04-05 14:54:58 -07:00
Alec Vercruysse
4993b1b426
turn off ce coverage for ram1p1rwe
...
According to the textbook, the cache memory chip enable,
`CacheEn`, is only lowered by the cachefsm with it is in the ready
state and a pipeline stall is asserted.
For read only caches, cache writes only occur in the state_write_line
state. So there is no way that a write would happen while the chip
enable is low.
Removing the chip-enable check from this memory to increase coverage
would be a bad idea since if anyone else uses this ram, the behaviour
would be differently than expected. Instead, I opted to turn off
coverage for this statement. Since this ram, which does not have a
byte enable, is used exclusively by read-only caches right now, this
should not mistakenly exclude coverage for other cases, such as D$.
2023-04-05 11:48:18 -07:00
Alec Vercruysse
277f507e9a
add ram1p1rwe for read-only cache ways (remove byte-enable)
...
- increases coverage
2023-04-05 11:48:18 -07:00
Ross Thompson
730f3ac84e
Fixed all tap/space issue in RTL.
2023-03-24 17:32:25 -05:00
David Harris
f8ad1b3db8
Improved IEU and bitmanip test coverage
2023-03-23 14:24:41 -07:00
David Harris
081a817925
Merge pull request #98 from ross144/main
...
New gshare implementation
2023-02-20 11:27:47 -08:00
David Harris
df9950483e
Removed unused and incomplete ROM macro instantations
2023-02-20 05:59:57 -08:00
Ross Thompson
0d79c0cebe
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-02-19 22:54:27 -06:00
David Harris
6d405ad69b
Fixed RAM instantiations
2023-02-19 06:31:41 -08:00
David Harris
a194740562
Fixed RAM bugs and refactored with read taking place after clock edge rather than before.
2023-02-17 19:14:38 -08:00
David Harris
9275bfb839
Memory synthesis updates
2023-02-17 15:33:49 -08:00
David Harris
2060683770
Continue fixing memory macros for synthesis
2023-02-17 15:15:37 -08:00
David Harris
3523318acb
Synthesis with memories
2023-02-17 13:51:05 -08:00
Ross Thompson
27f6552315
keep this commit off of cvw.
2023-02-16 11:05:24 -06:00
James Stine
744991bd5a
Update if-then-else for ram items
2023-02-15 18:12:12 -06:00
Kevin Kim
c59dfc1e30
fixed typo in LZC
2023-02-11 19:59:03 -08:00
David Harris
aae035226f
Merged with memories
2023-02-02 14:50:46 -08:00
David Harris
99d179dd3e
Removed pipelined level of hierarchy
2023-02-02 14:14:11 -08:00
