Ross Thompson
6c8ac7851e
Reverted to fetched the demand cache line first then doing the eviction. This is important because of an optimization in the replacement policy. The replacement policy updates the LRU 1 cycle late and reads the LRU 1 cycle late for critical path timing. This means doing the eviction first requires an initial 1 cycle delay but this delay has to be applied to all misses because we don't know if an eviction is required. Since reading the demand line first is logically ok so long as it is not written to the sram until after the eviction.
2022-07-19 22:42:25 -05:00
Ross Thompson
ffda64587c
Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.
2022-07-18 23:37:18 -05:00
Ross Thompson
396f697d2f
Hacky fix to prevent ITLBMissF and TrapM bug.
2022-04-12 17:56:23 -05:00
Ross Thompson
7b96b3f73c
Moved cacheable signal into cache.
2022-03-08 16:34:02 -06:00
Ross Thompson
7ffbc6b2ab
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
a5ad4331ec
More cache cleanup.
2022-02-13 12:38:39 -06:00
Ross Thompson
dd944265aa
Formating improvements to cache.
2022-02-11 23:10:58 -06:00
Ross Thompson
bf173b035c
More cache simplifications.
2022-02-11 22:54:05 -06:00
Ross Thompson
16abe90a0d
Reduced seladr to 1 bit as second bit is same as selflush.
2022-02-11 22:41:36 -06:00
Ross Thompson
b11e9eca7b
Reduced complexity of the address selection during flush.
2022-02-11 22:27:27 -06:00
Ross Thompson
1255e82154
Removed redundant signals from cache.
2022-02-11 22:23:47 -06:00
Ross Thompson
52894a7a4f
Cache fsm simplifications.
2022-02-11 15:16:45 -06:00
Ross Thompson
e2e0a4f595
Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY.
2022-02-11 15:09:00 -06:00
Ross Thompson
0f2ac0cb24
Simplified cache fsm.
2022-02-11 14:54:57 -06:00
Ross Thompson
1c83914662
Fixed bug.
...
It was possible for DTLBMissM to prevent a dcache flush.
2022-02-11 14:00:01 -06:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
Ross Thompson
754bd41fde
Cleaned up comments.
2022-02-09 19:21:35 -06:00
Ross Thompson
36ab78ef3b
Removed all possilbe paths to PreSelAdr from TrapM.
2022-02-09 19:20:10 -06:00
Ross Thompson
7810a09782
Annotated the final changes required to move sram address off the critial path.
2022-02-08 18:17:31 -06:00
Ross Thompson
4a7ebb3757
Cache cleanup write enables.
2022-02-08 17:52:09 -06:00
Ross Thompson
da2dca9816
Removed VDWriteEnable.
2022-02-07 21:59:18 -06:00
Ross Thompson
359a23237d
Progress towards simplifying the cache's write enables.
2022-02-07 17:23:09 -06:00
Ross Thompson
188fe28691
more cleanup.
2022-02-07 13:29:19 -06:00
Ross Thompson
9510a33c15
More cachefsm cleanup.
2022-02-07 13:19:37 -06:00
Ross Thompson
708e0cf183
More cachefsm cleanup.
2022-02-07 12:30:27 -06:00
Ross Thompson
5539a5fa6f
More cachefsm cleanup.
2022-02-07 11:16:20 -06:00
Ross Thompson
6668956351
More cachefsm cleanup.
2022-02-07 11:12:28 -06:00
Ross Thompson
5536e3ca90
More cachefsm cleanup.
2022-02-07 10:54:22 -06:00
Ross Thompson
529d8b629a
Cache cleanup.
2022-02-07 10:43:58 -06:00
Ross Thompson
41a79556e0
More cachfsm cleanup.
2022-02-07 10:33:50 -06:00
Ross Thompson
0b66106925
More cachefsm cleanup.
2022-02-06 21:50:44 -06:00
Ross Thompson
dd6baa9ed4
started cachefsm cleanup.
2022-02-06 21:39:38 -06:00
Ross Thompson
d21be9d998
Added config to allow using the save/restore or replay implementation to handle sram clocked read delay.
2022-02-04 23:49:07 -06:00
Ross Thompson
725852362e
Got separate module for the sub cache line read.
2022-02-04 20:23:09 -06:00
Ross Thompson
7c1f7e335c
Working first cut of the cache changes moving the replay to a save/restore.
...
The current implementation is too expensive costing (tag+linelen)*numway flip flops and muxes.
2022-02-04 13:31:32 -06:00
David Harris
ee3300bcd2
sram1rw cleanup
2022-02-03 18:03:22 +00:00
Ross Thompson
42ef1e22e5
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
Ross Thompson
e1db967417
Clean up of cachefsm.
2022-01-06 16:32:49 -06:00
Ross Thompson
365b2715ed
More name cleanup in cache.
2022-01-05 22:37:53 -06:00
Ross Thompson
8d33bf0b4a
Slower but correct implementation of flush.
2022-01-05 16:57:22 -06:00
Ross Thompson
49eea2add5
Fixed bug with flush dirty not cleared in the correct cache line.
2022-01-05 14:14:01 -06:00
Ross Thompson
f89c1d91dc
Renamed most signals inside cache.sv so they are agnostic to i or d.
2022-01-04 23:52:42 -06:00
