Ross Thompson
6c6b7865fb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-07 13:12:59 -06:00
Ross Thompson
22721dd923
Added generate around the dtim preload.
...
Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
29743c5e9e
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
bbracker
5a73ecd0be
regression.py bugfix
2021-12-06 19:32:38 -08:00
bbracker
4df9093a7f
add make-tests scripts
2021-12-06 15:37:33 -08:00
bbracker
7c44ecb364
add buildroot-only option to regression
2021-12-06 14:13:58 -08:00
bbracker
524bb0aa9a
linux-testvectors symlinks shouldn't be in repo, especially not in this location
2021-12-05 22:03:51 -08:00
Ross Thompson
c3c9c327b7
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
David Harris
f45fe48158
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-04 20:26:01 -08:00
David Harris
64f33161bc
Added files to repo
2021-12-04 20:25:33 -08:00
Skylar Litz
546f7fb4c2
fix some interrupt timing bugs
2021-12-03 12:32:38 -08:00
Ross Thompson
500e6ff430
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
b03ca464f1
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
9ccc8e7f3a
Merge branch 'fpga' into main
2021-12-02 14:28:10 -06:00
kwan
5164129172
.* resolved in ifu.sv
2021-12-02 10:32:35 -08:00
kwan
05a838aee2
.* in ifu/ifu.sv eliminated
2021-12-02 09:45:55 -08:00
David Harris
42780ba40b
Added coremark scripts to regression directory
2021-12-01 09:08:06 -08:00
David Harris
a146d7a618
testing push
2021-11-30 11:20:09 -08:00
Ross Thompson
97c73f10ff
Fixed uart for FPGA config after merge. This still needs some work.
2021-11-29 16:07:54 -06:00
Ross Thompson
a871118116
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
fed0bb08d6
UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
2021-11-25 11:01:59 -08:00
Noah Limpert
09d3322a26
updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well
2021-11-24 23:22:04 -08:00
Noah Limpert
93b626ce2a
replaced .* instation of priv module on wallypiplinedhart
2021-11-24 22:58:59 -08:00
Noah Limpert
f36cc7a2a3
Made abhlite instation on wallypipehart more clear, updated spacing for consistency
2021-11-24 22:48:01 -08:00
Noah Limpert
5b7c969170
updated module instation of LSU on wallypiplinedhard
2021-11-24 22:09:39 -08:00
bbracker
23194c0308
fix parseState.py to correctly take in PMPCFG
2021-11-24 16:52:51 -08:00
Ross Thompson
1183aed049
Missed another change to uart.
2021-11-23 10:20:47 -06:00
Ross Thompson
3fc370654d
Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
2021-11-23 10:00:32 -06:00
Ross Thompson
f12e7e1b68
Added QEMU hack for initial LCR value in uart.
2021-11-22 15:23:19 -06:00
Ross Thompson
f05a66acd1
Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed.
2021-11-22 15:20:54 -06:00
Ross Thompson
d5cf6da6eb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-22 11:30:14 -06:00
bbracker
cffb72042a
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Ross Thompson
e955b17500
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:44:45 -06:00
Ross Thompson
055a5bd202
Removed unneeded check for icache ways.
2021-11-20 22:44:37 -06:00
Ross Thompson
9d3261ed49
Reversed bit order in uart.
2021-11-20 22:43:05 -06:00
Ross Thompson
88b4e0946f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:37:15 -06:00
Ross Thompson
705572f0ac
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
bbracker
4e96d0f1db
add checkpoints to regression
2021-11-20 19:42:53 -08:00
bbracker
e5d3416258
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-19 20:25:06 -08:00
bbracker
713aa7faac
automatic bug finder script
2021-11-19 20:25:00 -08:00
bbracker
c07caf4fe8
increase buildroot progress expecttions; increase timeout to 20 hours
2021-11-19 12:52:11 -08:00
David Harris
82cfebfb83
Coremark Cleanup, trying compile from addins
2021-11-19 06:09:04 -08:00
David Harris
a801e0dbec
Moved exe2memfile.pl
2021-11-18 20:32:13 -08:00
David Harris
690410721d
Cleaning up CoreMark benchmark
2021-11-18 20:12:52 -08:00
David Harris
8e8b84f532
vert "Simplifying riscv-coremark"
...
This reverts commit ce8232e396
2021-11-18 18:40:13 -08:00
David Harris
ce8232e396
Simplifying riscv-coremark
2021-11-18 17:15:40 -08:00
David Harris
b73e6354e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-18 16:14:42 -08:00
David Harris
402b473dbb
CoreMark testing
2021-11-18 16:14:25 -08:00
slmnemo
0bf1836a3a
Removed .* from hazard hzu(.*).
2021-11-17 14:21:23 -08:00
