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197 Commits

Author SHA1 Message Date
Thomas Fleming
bfb4b051c6 Merge branch 'main' into mmu 2021-04-01 16:29:39 -04:00
Thomas Fleming
350fe87119 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-04-01 16:24:06 -04:00
Thomas Fleming
fdb20ee1cf Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
James E. Stine
0495195d68 Fixed some divide -still bug in AHB causing InstStall to deassert and next instruction to get into divide unit. Hope to fix soon. Divide seems to work if given enough time. 2021-04-01 12:30:37 -05:00
Thomas Fleming
77b8e27205 Disable 'always-on' virtual memory 2021-03-30 22:49:47 -04:00
Thomas Fleming
eca2427f94 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
7126ab7864 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
6b9ae41302 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Brett Mathis
162f2df880 FPU Pipeline completed - can begin integration 2021-03-25 13:29:03 -05:00
Thomas Fleming
e3900bd0fa Finish finite state machines for page table walker 2021-03-25 02:48:40 -04:00
Thomas Fleming
b5003b093a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-25 02:35:21 -04:00
bbracker
a3788eb218 added 1 tick delay to dtim flops 2021-03-25 02:23:30 -04:00
bbracker
02e924e55a instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
bbracker
1e3f683a9d upgraded gpio bus interface 2021-03-25 00:15:02 -04:00
bbracker
e98dd420bc future work comment about suspicious-looking verilog in csri.sv 2021-03-25 00:10:44 -04:00
Thomas Fleming
b1d849c822 Add all PMP addr registers 2021-03-24 21:58:33 -04:00
Katherine Parry
18cb1f4873 fixed various bugs in the FMA 2021-03-24 21:51:17 +00:00
Katherine Parry
56dc8de009 fixed various bugs in the FMA 2021-03-24 01:35:32 +00:00
Teo Ene
ef3d2dda48 Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem 2021-03-23 15:21:13 -05:00
Shreya Sanghai
1d6a2989ed PC counts branch instructions 2021-03-23 14:25:51 -04:00
bbracker
5efd5958e7 added delays to uart AHB signals 2021-03-22 15:40:29 -04:00
bbracker
11d4a8ab34 first pass at PLIC interface 2021-03-22 10:14:21 -04:00
Katherine Parry
f741ba7702 fixed various bugs in the FMA 2021-03-21 22:53:04 +00:00
Katherine Parry
e317e7511e messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic 2021-03-20 02:05:16 +00:00
bbracker
85363e941d AHB bugfixes and sim waveview refactoring 2021-03-18 18:25:12 -04:00
Shreya Sanghai
bbe0957df5 Merge branch 'gshare' into main 
Conflicts:
	wally-pipelined/regression/wave.do
 2021-03-18 17:25:48 -04:00
Ross Thompson
1091dd10c1 Switched to gshare from global history. 
Fixed a few minor bugs.
 2021-03-18 16:05:59 -05:00
Ross Thompson
8f4051543c Fixed minor bug with the size of gshare. 2021-03-18 16:00:09 -05:00
Shreya Sanghai
eb86bfc084 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
8d484174a7 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-18 14:36:42 -04:00
Thomas Fleming
7f7597e667 Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Noah Boorstin
bc1a0c6ee7 change ifndef to generate/if 2021-03-18 12:50:19 -04:00
Noah Boorstin
a2b0af460e everyone gets a bootram 2021-03-18 12:35:37 -04:00
Shreya Sanghai
36f0631203 added gshare and global history predictor 2021-03-16 17:03:01 -04:00
Shreya Sanghai
9eed875886 added global history branch predictor 2021-03-16 16:06:40 -04:00
Shreya Sanghai
08e9149e20 made performance counters count branch misprediction 2021-03-16 11:24:17 -04:00
Shreya Sanghai
74f1641c5a Merge branch 'counters' into main 
added a configurable number of performance counters
 2021-03-16 11:01:30 -04:00
bbracker
345254b5a3 slightly smarter dtim HREADY 2021-03-13 06:55:34 -05:00
bbracker
c5015e5809 imem rd2 adrbits bugfix 2021-03-13 00:10:41 -05:00
bbracker
f4fb546969 clint HREADY signal update 2021-03-12 20:23:55 -05:00
Ross Thompson
6ee97830f7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
7743d8edc3 Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
David Harris
865c103599 64-bit AMO debugged 2021-03-11 23:18:33 -05:00
Thomas Fleming
1294235837 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ebu/ahblite.sv
 2021-03-11 00:15:58 -05:00
David Harris
42275e92ed Initial untested implementation of AMO instructions 2021-03-11 00:11:31 -05:00
Noah Boorstin
2c25e270a2 change flop in ahb controller to use normal flop module 2021-03-10 19:14:02 +00:00
David Harris
17c0f9629a WALLY-LRSC atomic test passing 2021-03-09 09:28:25 -05:00
David Harris
9c7da510fb Created atomic test vector and directories 2021-03-08 09:38:55 -05:00
Ross Thompson
87ed6d510c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-05 15:27:22 -06:00
Ross Thompson
301166d062 Oups. I forgot to update other do files with the commands to preload the branch predictor memories. 2021-03-05 15:23:53 -06:00