David Harris
c1786bfec8
IMMU exclude non word-sized accesses
2023-05-01 08:14:19 -07:00
David Harris
bfa35d727b
Fixed redundant check of SupportedFmt on fmv that caused coverage problem on fctrl
2023-04-29 05:58:40 -07:00
David Harris
d5c350c597
Merged coverage exclusions for PMP
2023-04-28 08:04:25 -07:00
David Harris
ca5a71bbe5
PMA Checker coverage
2023-04-28 07:53:59 -07:00
David Harris
22e4f82a99
Commenting
2023-04-28 07:52:08 -07:00
David Harris
f6f43e826a
Removed clear from TLBLRU because there is no need to flush LRU state and it causes coverage issues
2023-04-28 07:03:46 -07:00
David Harris
e962e95e53
CSR code cleanup
2023-04-27 14:12:57 -07:00
David Harris
e519eaa33f
Renamed byteUnit to byteop
2023-04-27 14:10:46 -07:00
Liam
6803347a49
Pmpadrdecs test cases changing AdrMode to 2 or 3
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Setting AdrMode to 2 or 3 for pmpadrdecs[0-4] writing values to pmpcfg0 to change AdrMode to 2 or 3
Also exclusion for pmpadrdecs[0] coverage case for PAgePMPAdrIn being hardwired to 1 in pmpadrdec.sv
2023-04-27 12:23:35 -07:00
David Harris
e69ebc45c0
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-27 07:30:07 -07:00
Alexa Wright
667c54c129
Merge branch 'openhwgroup:main' into main
2023-04-26 16:26:30 -07:00
Alexa Wright
79031e3de0
Added better comment for the exclusion in privdec.sv
2023-04-26 16:25:55 -07:00
David Harris
7c1a4e5e32
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-26 15:40:11 -07:00
David Harris
0ad5165795
Merge pull request #283 from SydRiley/main
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Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
2023-04-26 15:40:01 -07:00
Sydeny
4595c22fe1
Addressing Redundant logic around BadNanBox, fpu coverage from 96.61% to 96.77%
2023-04-26 14:35:43 -07:00
David Harris
d71d84b386
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-26 05:53:42 -07:00
Alec Vercruysse
6299c0ef0b
Cacheway Exclude FlushStage=1 when SetValidWay=1
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We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).
My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
2023-04-25 20:30:46 -07:00
Alexa Wright
55a74fd315
Excluded and added coverage for WFI test case.
2023-04-25 17:06:57 -07:00
Alec Vercruysse
2f49ee18fe
Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign
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FlushWay is always 1 for one way, but by default it is only 1 for
way 0.
The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
2023-04-25 17:02:53 -07:00
David Harris
03448aa691
Commented about Sstvecd trap vector alignment
2023-04-24 12:20:33 -07:00
David Harris
8bf9329815
Added M suffix in atomic
2023-04-24 12:19:56 -07:00
Diego Herrera Vicioso
c681789296
Excluded coverage for impossible cases in wficountreg and status.MPRV
2023-04-24 02:06:53 -07:00
David Harris
1d532dfcfc
Fault on writes to odd-numbered PMPCFG in RV64
2023-04-22 15:32:39 -07:00
David Harris
a5b80bc440
Removed unproven fdivsqrt exclusion
2023-04-22 15:27:05 -07:00
David Harris
8be5ed9b67
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
David Harris
0871bbe8f2
Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right
2023-04-22 10:07:48 -07:00
David Harris
e11212598f
fdivsqrt cleanup
2023-04-20 17:35:01 -07:00
David Harris
f9ca280e01
continued cleanup
2023-04-20 16:48:23 -07:00
David Harris
ea7c50e0ee
Reordered fdivsqrtpreproc to follow logic
2023-04-20 16:38:47 -07:00
David Harris
ca0269c094
Started fdivsqrtpreproc flow organization
2023-04-20 16:25:19 -07:00
David Harris
c431278fe6
Fmv h/q comments in controller
2023-04-20 16:24:58 -07:00
David Harris
94d1533264
Merge pull request #256 from cturek/main
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Simplifying fds to follow diagram
2023-04-20 16:07:22 -07:00
David Harris
24e60c232d
Merge pull request #262 from SydRiley/main
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removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 14:49:50 -07:00
Sydeny
b76ed145e6
removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 13:30:12 -07:00
Alec Vercruysse
7ba2bfd4b6
CacheFSM logic simplification for AMO operations
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Ran this by Ross.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
b52512b1ae
D$ scope-specific coverage exclusions (I$ logic that never fires)
...
The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.
Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.
There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Cedar Turek
30bd1e2a33
created fdivsqrtcycles, moved cycles calculation from FSM to preproc
2023-04-18 16:14:45 -07:00
Cedar Turek
871d495ca1
gave integer bits to D instead of adding manually everywhere
2023-04-18 15:41:04 -07:00
Cedar Turek
054c8d638c
moved D flop to preproc
2023-04-18 15:14:17 -07:00
Sydeny
4748fa0f6b
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-17 13:51:16 -07:00
David Harris
bdd5f5e611
Merge pull request #251 from masonadams25/main
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Removed redundent expression to increase coverage
2023-04-17 12:37:27 -07:00
Mason Adams
4468086e06
Removed redundent expression to increase coverage
2023-04-17 14:13:26 -05:00
David Harris
b00b8ba366
merged coverage exclusions
2023-04-17 10:17:48 -07:00
Diego Herrera Vicioso
34dd481f93
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Sydeny
af51b6f16c
trimming comments on fctrl bug fixes
2023-04-15 00:48:32 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3
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Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116
replace instances of code duplication for i$ exclusions w/commands
2023-04-14 17:10:39 -07:00
Limnanthes Serafini
5952a4b0a3
Final small fix
2023-04-14 14:15:52 -07:00
Limnanthes Serafini
34aedc4f79
indent fix
2023-04-14 14:14:34 -07:00
Limnanthes Serafini
95223bf11c
More cleanup
2023-04-13 21:34:50 -07:00
