Ross Thompson
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002c32d2ad
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The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
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2021-06-30 17:02:36 -05:00 |
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Ross Thompson
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dd84f2958e
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Page table walker now walks the table.
Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
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2021-06-29 22:33:57 -05:00 |
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Ross Thompson
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f74ecbb81e
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Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
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2021-06-23 15:13:56 -05:00 |
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Ross Thompson
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f79e5eaa47
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Icache now uses physical lenght bits rather than XLEN.
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2021-06-21 16:41:09 -05:00 |
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Ross Thompson
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3cbe4c9bc2
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Improved some names in icache.
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2021-06-21 16:40:37 -05:00 |
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Ross Thompson
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70c45a5349
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Revert "Icache now uses physical lenght bits rather than XLEN."
This reverts commit 16266d978a.
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2021-06-19 08:58:34 -05:00 |
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Ross Thompson
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868ddce5f2
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Revert "Improved some names in icache."
This reverts commit a57c63aa7b.
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2021-06-19 08:58:32 -05:00 |
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Ross Thompson
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a57c63aa7b
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Improved some names in icache.
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2021-06-18 12:22:41 -05:00 |
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Ross Thompson
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16266d978a
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Icache now uses physical lenght bits rather than XLEN.
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2021-06-18 12:02:59 -05:00 |
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David Harris
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c6ff11c22e
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disabled Verilator WIDTH warnings in ICCacheCntrl
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2021-06-12 19:50:06 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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Ross Thompson
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7406e33b61
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Continued I-Cache cleanup.
Removed strange mux on InstrRawD along with
the select logic.
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2021-06-04 15:14:05 -05:00 |
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Ross Thompson
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fdef8df76b
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Reorganized the icache names.
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2021-06-04 12:53:42 -05:00 |
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