Domenico Ottolia
|
56a32b5882
|
More bug fixes for privileged tests
|
2021-03-25 15:05:55 -04:00 |
|
Jarred Allen
|
3b4f0141f4
|
Begin work on compressed instructions
|
2021-03-25 14:43:10 -04:00 |
|
Noah Boorstin
|
44060b579b
|
busybear: quick fix to mem reading
also stop ignoring mcause at the start
|
2021-03-25 14:29:11 -04:00 |
|
Brett Mathis
|
162f2df880
|
FPU Pipeline completed - can begin integration
|
2021-03-25 13:29:03 -05:00 |
|
Domenico Ottolia
|
f134b09a97
|
Fix bugs with privileged tests
|
2021-03-25 14:06:05 -04:00 |
|
Noah Boorstin
|
d02c88dab5
|
busybear: stop NOPing out atomics
and bump regression to check for 800k instrs, up from 200k
|
2021-03-25 13:29:56 -04:00 |
|
David Harris
|
ee36f4e09b
|
Added WALLY-PIPELINE test to rv64wally
|
2021-03-25 13:18:50 -04:00 |
|
Jarred Allen
|
0290568a52
|
Make cache output NOP after a reset
|
2021-03-25 13:18:30 -04:00 |
|
David Harris
|
eb9787609e
|
testgen-PIPELINE python startup
|
2021-03-25 13:12:18 -04:00 |
|
Shriya Nadgauda
|
21989ee615
|
adding PIPELINE tests
|
2021-03-25 13:07:25 -04:00 |
|
Jarred Allen
|
ce6f102fc5
|
Clean up some stuff
|
2021-03-25 13:04:54 -04:00 |
|
Jarred Allen
|
128278ea27
|
Working for all of rv64i now, but not compressed instructions
|
2021-03-25 13:02:26 -04:00 |
|
Jarred Allen
|
602271ff7b
|
rv64i linear control flow now working
|
2021-03-25 13:02:26 -04:00 |
|
Jarred Allen
|
ba95557c44
|
More progress on icache controller
|
2021-03-25 13:01:11 -04:00 |
|
Jarred Allen
|
ad0d77e9e1
|
Begin rewrite of icache module to use a direct-mapped scheme
|
2021-03-25 13:01:10 -04:00 |
|
Jarred Allen
|
ebd6b931c6
|
Fix bug in cache line
|
2021-03-25 12:59:30 -04:00 |
|
Jarred Allen
|
b774d35c34
|
Output NOP instead of BAD when reset
|
2021-03-25 12:42:48 -04:00 |
|
Jarred Allen
|
4b92a595ab
|
Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/uncore/dtim.sv
|
2021-03-25 12:10:26 -04:00 |
|
Teo Ene
|
51291949d8
|
Config file for ppa experiments
|
2021-03-25 10:23:21 -05:00 |
|
David Harris
|
a8abd47fbc
|
Added PPA README
|
2021-03-25 11:21:31 -04:00 |
|
Thomas Fleming
|
e3900bd0fa
|
Finish finite state machines for page table walker
|
2021-03-25 02:48:40 -04:00 |
|
Thomas Fleming
|
7367052e76
|
Add vscode and pycache folders to .gitignore
|
2021-03-25 02:37:50 -04:00 |
|
Thomas Fleming
|
b5003b093a
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-03-25 02:35:21 -04:00 |
|
bbracker
|
a3788eb218
|
added 1 tick delay to dtim flops
|
2021-03-25 02:23:30 -04:00 |
|
bbracker
|
b5fa410e15
|
added 1 tick delay on tim reads
|
2021-03-25 02:15:28 -04:00 |
|
Jarred Allen
|
682050a33b
|
Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/ifu/ifu.sv
|
2021-03-25 00:51:12 -04:00 |
|
bbracker
|
67b27cd2f5
|
instrfault direspecting stalls bugfix
|
2021-03-25 00:44:35 -04:00 |
|
bbracker
|
02e924e55a
|
instrfaults not respecting stalls bugfix
|
2021-03-25 00:16:26 -04:00 |
|
bbracker
|
1e3f683a9d
|
upgraded gpio bus interface
|
2021-03-25 00:15:02 -04:00 |
|
bbracker
|
717257d9ac
|
gitignore FunctionRadix.addr
|
2021-03-25 00:13:46 -04:00 |
|
bbracker
|
e98dd420bc
|
future work comment about suspicious-looking verilog in csri.sv
|
2021-03-25 00:10:44 -04:00 |
|
Thomas Fleming
|
b1d849c822
|
Add all PMP addr registers
|
2021-03-24 21:58:33 -04:00 |
|
Teo Ene
|
f5b70c8ab8
|
Manual assembly hack to prevent RV64IM coremark from EBREAKing early
|
2021-03-24 18:05:34 -05:00 |
|
Teo Ene
|
a3aa103dc7
|
Fix typo from last commit
|
2021-03-24 17:09:58 -05:00 |
|
Teo Ene
|
4427b5ec01
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
|
2021-03-24 17:04:48 -05:00 |
|
Teo Ene
|
e43849b82c
|
Updated coremark_bare testbench for IM
|
2021-03-24 17:04:43 -05:00 |
|
Katherine Parry
|
18cb1f4873
|
fixed various bugs in the FMA
|
2021-03-24 21:51:17 +00:00 |
|
Teo Ene
|
385ce9a8f9
|
Added BPTYPE to coremark_bare config
|
2021-03-24 16:38:29 -05:00 |
|
Ross Thompson
|
a99c0502e5
|
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
|
2021-03-24 15:56:55 -05:00 |
|
Ross Thompson
|
11109e5a88
|
Updated the function radix to have a new name FunctionName and it now pervents false transisions from the current function name when the PCD is flushed.
|
2021-03-24 13:03:43 -05:00 |
|
Domenico Ottolia
|
d67e28bf50
|
re-organize privileged tests to be in rv64p to rv32p folders
|
2021-03-24 13:51:25 -04:00 |
|
Jarred Allen
|
c1fe16b70b
|
Give some cache mem inputs a better name
|
2021-03-24 12:31:50 -04:00 |
|
Ross Thompson
|
d74b6eb69c
|
Updated the .gitignore to reject all the extra compiled objects for the branchmarks.
|
2021-03-24 10:30:19 -05:00 |
|
Ross Thompson
|
efa8ad4e17
|
Edited sieve to work with wally. It was using the time of day to compute runspeed; however this functionality does not yet work in the wally software stack.
|
2021-03-24 09:22:21 -05:00 |
|
Jarred Allen
|
a51257abca
|
Fix compile errors from const not actually being constant (why does Verilog do this)
|
2021-03-24 00:58:56 -04:00 |
|
Ross Thompson
|
1c6e37120e
|
Fixed RAS errors. Still some room for improvement with the BTB and RAS.
|
2021-03-23 23:00:44 -05:00 |
|
Jarred Allen
|
4410944049
|
Merge branch 'main' into cache
|
2021-03-23 23:35:36 -04:00 |
|
Ross Thompson
|
84ad1353e4
|
Fixed a bunch of bugs with the RAS.
|
2021-03-23 21:49:16 -05:00 |
|
Katherine Parry
|
56dc8de009
|
fixed various bugs in the FMA
|
2021-03-24 01:35:32 +00:00 |
|
Ross Thompson
|
4fb7a1e0a6
|
Fixed the valid bit issue. Now the branch predictor is actually predicting instructions.
|
2021-03-23 20:20:23 -05:00 |
|