14 Commits

Author	SHA1	Message	Date
David Harris	f441c8e16a	Fixed lint for RV32IC by handling PMP_ENTRIES = 0 in csrm, but may have broken buildroot.	2021-12-30 02:38:42 +00:00
David Harris	d8ba97cf71	RV32ic tests running for simple machine with no privileged unit	2021-12-30 02:25:46 +00:00
David Harris	98aaa970dd	rv32i regression and linting	2021-12-30 00:53:39 +00:00
David Harris	52a38c5856	Added performance counting to sumtest and added imperas32/64periph to testbench.	2021-12-29 00:28:51 +00:00
David Harris	e6ed1372a7	Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.	2021-12-26 04:36:53 +00:00
David Harris	48bb534658	Started FIR test code and started incorporating Imperas tests	2021-12-25 22:39:51 +00:00
David Harris	865d5ce0b1	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
David Harris	2039752740	Simplified ALU and source multiplexers pass tests	2021-12-13 07:57:38 -08:00
David Harris	402b473dbb	CoreMark testing	2021-11-18 16:14:25 -08:00
David Harris	247f247ad3	tesgen cleanup, added riscv-arch-test D tests	2021-10-29 22:31:48 -07:00
David Harris	5783e47e1a	Changes for floating point sims	2021-10-27 10:37:35 -07:00
David Harris	75c17dc372	Major reorganization of regression and simulation and testbenches	2021-10-10 15:07:51 -07:00
Ross Thompson	f070aae847	Fixed issue with sim-wally-batch. Are people still using this script?	2021-03-17 11:17:52 -05:00
David Harris	fa18052348	Added test configurations	2021-01-25 11:28:43 -05:00