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Author SHA1 Message Date
bbracker
c697c17b05 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-13 05:35:56 -07:00
bbracker
016e960401 change interrupt spoofing to happen at negative clock edges 2022-04-13 04:31:23 -07:00
bbracker
3465d8cd32 improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS 2022-04-13 03:37:53 -07:00
bbracker
0d4ec9b3f9 fix bugs in PLIC checkpoint state parsing 2022-04-13 01:59:21 -07:00
bbracker
1bb5e1f35b whoops fix address for PLIC int enables in checkpoint generation 2022-04-13 01:36:09 -07:00
bbracker
67ef47b25b whoops forgot to update AttemptedInstructionCount in interrupt spoofing 2022-04-13 00:49:37 -07:00
bbracker
6c3d274970 change testbench-linux to by default use attempted instruction count for warning/error messages 2022-04-12 21:22:08 -07:00
Ross Thompson
2eb2263e94 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 19:38:04 -05:00
Ross Thompson
adb4e30c45 Missed the force on uart for no tracking. 2022-04-12 19:37:44 -05:00
Ross Thompson
d087deef65 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-12 17:56:48 -05:00
Ross Thompson
22f2e88553 UART and clock speed changes to support 30Mhz. 2022-04-12 17:56:36 -05:00
Ross Thompson
396f697d2f Hacky fix to prevent ITLBMissF and TrapM bug. 2022-04-12 17:56:23 -05:00
Ross Thompson
70e207e010 Found the complex TrapM giving back the wrong instruction bug. 
As I was reviewing the busfsm I found a typo.

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

It should be

  assign UnCachedLSUBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & LSURWM[1] & ~IgnoreRequest) |
							  (BusCurrState == STATE_BUS_UNCACHED_READ);

There is a ~ missing before IgnoreRequest. I restarted the FPGA and had it trigger on the specific faulting event.  Sure enough the bus makes an IFUBusRead, which UncachedLSUBusRead feeds into.   The specific instruction in the fetch stage had an ITLBMiss with a physical address in an unmapped area which is interpreted as an uncached operation.  IgnoreRequest is is high if there is a TrapM | ITLBMissF.  Without the & ~IgnoreRequest the invalid address translation makes the request.
 2022-04-11 13:07:52 -05:00
Ross Thompson
56bea58a3c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-10 13:41:27 -05:00
Ross Thompson
fc5eac6820 Modified the linux test bench to take a new parameter which can run simulation from 470M out to login prompt. This shouldn't break the regression test or checkpointing. 2022-04-10 13:27:54 -05:00
bbracker
c0c5733a1d upgrade testbench interrupt forcing such that first m_timer interrupt now successfully spoofs 2022-04-08 13:45:27 -07:00
bbracker
23406d0926 small signs of life on new interrupt spoofing 2022-04-08 12:32:30 -07:00
bbracker
a09360f207 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-07 19:43:27 -07:00
bbracker
54c5f7f607 deprecate remove_dup.awk in favor of expanding parseGDBtoTrace.py to internally remove duplicates; this way the instruction counts in traps.txt are hopefully now in sync with the line numbers of all.txt 2022-04-07 19:43:22 -07:00
Ross Thompson
9685365d2e Added signals to ila. 2022-04-07 21:09:50 -05:00
Ross Thompson
6702e2c735 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-07 16:56:56 -05:00
Ross Thompson
de868ef3a2 Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction. 2022-04-07 16:56:28 -05:00
Ross Thompson
22279a29ab Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-07 16:29:48 -05:00
Ross Thompson
54de15752e Added sp to ila. 2022-04-07 16:29:41 -05:00
Ross Thompson
1614996941 Fixed typo in tests.vh 2022-04-07 16:28:28 -05:00
Katherine Parry
3224512812 re-adding an empty 'vectors' folder 2022-04-07 17:44:08 +00:00
Katherine Parry
72e4ab8361 cleaned floating point 'vectors' folder 2022-04-07 17:31:08 +00:00
Katherine Parry
74e0db04ac fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
bbracker
008089b470 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-07 08:37:44 -07:00
bbracker
0a0956fad0 fix parseQEMUtoGDB.py to pass on interrupt messages correctly 2022-04-07 04:47:15 -07:00
kaveh Pezeshki
49aae4b2e9 using -S for busybox objdump to provide source code snippets 2022-04-06 23:06:49 +00:00
bbracker
0f394ba18b Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-06 07:50:57 -07:00
bbracker
0a8ce0593a filter traps list down to just interrupts 2022-04-06 07:49:44 -07:00
bbracker
ea0471dcc7 change RAM size in genInitMem.sh 2022-04-06 07:49:04 -07:00
Kip Macsai-Goren
c3a6b88acc updated test signature locations 2022-04-06 07:28:38 +00:00
Kip Macsai-Goren
590b86147b Updated trap handler to check interrupt vectoring before handling them and to use the mscratch instead of sp for a stack. 2022-04-06 07:13:51 +00:00
Kip Macsai-Goren
3268f27f7a Updated PMA tests to comply with all width writes and reads to CLINT 2022-04-06 07:13:51 +00:00
Kip Macsai-Goren
fbcb0c0bd8 Added missing ZFH macro to new configs 2022-04-06 07:13:51 +00:00
David Harris
7f462a6168 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-04-05 23:23:47 +00:00
David Harris
23da303ad3 Added bootmem source ccode 2022-04-05 23:22:53 +00:00
Ross Thompson
900939581e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-05 15:42:07 -05:00
Ross Thompson
5faa88acd5 Increazed fpga clock speed to 35Mhz. 
linux boot is much faster.
 2022-04-05 15:09:49 -05:00
David Harris
171b943254 Removed outdated sample testfloat calls 2022-04-04 17:23:39 +00:00
Katherine Parry
c3d07b2c46 generating all testfloat vectors 2022-04-04 17:17:12 +00:00
Ross Thompson
91e99f0d34 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-04 10:56:10 -05:00
Ross Thompson
077beb18dd Constraint changes for 40Mhz wally. 2022-04-04 10:50:48 -05:00
Ross Thompson
b77201143f Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash. 2022-04-04 10:38:37 -05:00
Ross Thompson
400b5f7632 Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz. 2022-04-04 09:57:26 -05:00
Ross Thompson
38160fe6ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-04-03 17:56:55 -05:00
Ross Thompson
3ebb7f1057 fpga simulation works again. 2022-04-03 17:31:07 -05:00