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81 Commits

Author SHA1 Message Date
bbracker
742e8d98cd fix up PLIC and UART checkpointing 2022-03-07 23:48:47 -08:00
bbracker
92e1583db5 change testbench-linux.sv to use new shared location of disassembly files 2022-03-07 20:04:08 -08:00
David Harris
e4d18f1808 removed more old 64priv tests 2022-03-04 03:57:19 +00:00
bbracker
c3e59ae2df comment out nonfunctioning CSR-PERMISSIONS-M test 2022-03-04 00:11:55 +00:00
bbracker
79ff8d3c80 remove imperas32p tests 2022-03-04 00:06:18 +00:00
bbracker
87aad1d953 fix peripheral test and add it to regression 2022-03-02 23:44:39 +00:00
bbracker
4fe35aadf2 add rv32a tests to regression 2022-03-02 17:54:55 +00:00
bbracker
b6031bb15f fix buildroot checkpointing and add it back to regression 2022-03-02 16:00:19 +00:00
bbracker
29179c6787 add LRSC test and add wally64a to regression 2022-03-02 07:09:37 +00:00
bbracker
a8e8cfb838 switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv 2022-03-01 03:11:43 +00:00
bbracker
d8ddda760b deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test 2022-03-01 00:37:46 +00:00
David Harris
329fea9329 Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath 2022-02-28 20:50:51 +00:00
bbracker
ac114e1c6d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-22 04:27:50 +00:00
bbracker
202bd2f8f8 change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests 2022-02-22 03:46:08 +00:00
Kip Macsai-Goren
04892c5d38 added scratch register tests for 64 and 32 bits 2022-02-21 07:03:12 +00:00
Kip Macsai-Goren
324efa7d42 added 32 bit pma tests to regression even though they've been working fo a while 2022-02-18 19:43:24 +00:00
Kip Macsai-Goren
dcb5d0f6a9 Added misa test for both 32 and 64 bits 2022-02-18 19:41:50 +00:00
Kip Macsai-Goren
e16581d73d added CSR permission and minfor to 32 bit tests 2022-02-15 20:19:14 +00:00
Kip Macsai-Goren
943c4d9d7c merged test macros in with 32 bit tests 2022-02-15 20:19:14 +00:00
David Harris
f734afb866 Just needed to recompile - all good. Now removed uretM because N-mode is depricated 2022-02-15 19:48:49 +00:00
Kip Macsai-Goren
9ff4025844 light cleanup for privileged tests 2022-02-15 17:06:16 +00:00
David Harris
64e9f4c0d3 Restored E tests to makefrag 2022-02-08 16:41:11 +00:00
David Harris
f00b3ac27e Fixed TIM tests; rv32e test still failing 2022-02-08 15:24:37 +00:00
David Harris
76dccbad91 Patching up testbench; fixed false passing, but rv32ic and rv32e tests now fail 2022-02-08 12:40:02 +00:00
David Harris
c61cd55c5c Merged TIM and regular testbenches. RV32e now working and back in regression. 2022-02-08 12:18:13 +00:00
David Harris
cbef88ec10 Lab 3 file cleanup 2022-02-08 10:26:37 +00:00
Kip Macsai-Goren
0eb280b314 added new tests to make and testbench 2022-02-06 19:47:22 +00:00
bbracker
f67af23bf3 remove sporadic tabs from tests.vh so that it is now only spaces 2022-02-05 23:07:38 +00:00
David Harris
72bc64ef28 Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests. 2022-02-05 04:16:18 +00:00
David Harris
2c67f32b97 RV32e tests 2022-02-04 14:30:36 +00:00
David Harris
a6708ed887 cache cleanup 2022-02-03 15:36:11 +00:00
David Harris
38bbe23d14 More config file cleanup; 32ic tests broken 2022-02-03 01:08:34 +00:00
David Harris
da8819d64b changed DMEM and IMEM configurations to support BUS/TIM/CACHE 2022-02-03 00:41:09 +00:00
David Harris
02071700d6 Removed Busybear dependencies 2022-02-02 20:28:21 +00:00
Ross Thompson
f4a553fd7d Fixed testbench so coremark stops. 2022-02-02 11:37:48 -06:00
Ross Thompson
4b4cee3ddd Added correct stop condition for coremark. 2022-02-02 09:53:51 -06:00
Ross Thompson
143bdaa288 Modified makefiles to generate function address to name mappings for modelsim. 2022-02-01 18:25:03 -06:00
Ross Thompson
f055441ecf Improved function_radix to not printout warnings when no valid function is found. 2022-02-01 18:03:09 -06:00
Ross Thompson
5407b72af9 Setup the main regression test to be able to handle coremark. 2022-02-01 17:00:11 -06:00
Ross Thompson
86bac2a083 partial ifu cleanup. 2022-01-31 16:08:53 -06:00
Ross Thompson
5ce8dd60c5 Fixed modelsim warning with linux simulation. 2022-01-31 12:57:02 -06:00
Ross Thompson
c2b2fae98d Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-31 12:17:37 -06:00
Ross Thompson
9cd502d0af Encapsulated dtim. 2022-01-31 11:23:55 -06:00
Kip Macsai-Goren
242b27705d added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
David Harris
090533cfe9 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
David Harris
7f91170bab Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
David Harris
21bdce63ff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
David Harris
07425369fc Renamed wallypipelinedhart to wallypipelinedcore 2022-01-20 16:02:08 +00:00
David Harris
b63e53bbdb Defined rv32e and rv32emc configs 2022-01-17 14:01:01 +00:00
David Harris
6febce0001 Moved Dcache into bus block 2022-01-15 00:39:07 +00:00