Ross Thompson
0782e5c5a6
Moved LSU Bus interface control path into it's own module.
2021-12-29 17:12:29 -06:00
Ross Thompson
1730f644af
Name cleanup in LSU.
2021-12-29 16:34:35 -06:00
Ross Thompson
050523487c
Changed names of lsu address signals.
2021-12-29 15:03:34 -06:00
Ross Thompson
846ed35e20
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-29 14:48:16 -06:00
Ross Thompson
b1116600fe
Added more generates around virtual memory and csrs in the lsu.
2021-12-29 14:48:09 -06:00
Kip Macsai-Goren
d0c0d633a1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 19:42:35 +00:00
James E. Stine
d2e6bb5674
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 13:01:27 -06:00
James E. Stine
15d38f8c7f
Add configuration for IEEE 754 or non IEEE 754 per RISC-V guidelines
...
Katherine/James
2021-12-29 12:59:17 -06:00
David Harris
3bd9343013
Fixed .gitignore
2021-12-29 18:58:36 +00:00
David Harris
a320fcfeb9
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 18:53:13 +00:00
David Harris
81b382e51e
Switched riscv-arch-test to current hash
2021-12-29 18:52:52 +00:00
Ross Thompson
bc437cf7e0
Cleaned up some names in dcache and lsu.
2021-12-29 11:21:44 -06:00
Ross Thompson
fe22d4544f
Converted mux4 to mux3 in dcache.
2021-12-29 10:58:02 -06:00
Ross Thompson
0c88ddeb5a
Simplified the dcache to bus address generation.
2021-12-29 10:46:48 -06:00
Ross Thompson
6052a69ba7
Fixed interrupt delay bug by reverting CommittedM changes.
2021-12-28 22:27:12 -06:00
Ross Thompson
86b5a46ab3
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-28 21:28:12 -06:00
Ross Thompson
1894afd0d8
Changed name of LSU's FetchCount to WordCount. This better reflex the dual usage as fetch and eviction counters.
...
Fixed bug with the uncached memory operations. The periph tests still do not pass. They enter into what seems an intentional infinite loop. Then a uart interrupt jumps into an ISR but the ISR returns back to the loop.
2021-12-28 21:28:03 -06:00
David Harris
f9ab193ca8
Added partially working MMU tests
2021-12-29 03:14:16 +00:00
Ross Thompson
71c069a25d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-28 20:22:36 -06:00
David Harris
e4b4800189
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-29 00:29:12 +00:00
David Harris
52a38c5856
Added performance counting to sumtest and added imperas32/64periph to testbench.
2021-12-29 00:28:51 +00:00
Ross Thompson
76d1dc1721
LSU Bus FSM beautification.
2021-12-28 16:53:53 -06:00
Ross Thompson
e29803be30
Removed CommittedM as it is redundant with LSUStall.
2021-12-28 16:14:10 -06:00
Ross Thompson
39bd78c295
Changed the bus name between dcache and ebu.
2021-12-28 15:57:36 -06:00
Ross Thompson
d62cd1f701
Reverted changes to subwordread while keeping the new names of the i/o.
2021-12-28 15:57:21 -06:00
Ross Thompson
9c190b019b
Name changes for states in LSU.
2021-12-28 15:03:24 -06:00
Ross Thompson
13b4201198
Added generate around virtual memory hardware in LSU.
2021-12-28 15:00:02 -06:00
Ross Thompson
f09b10a393
Moved generate for lrsc to lsu.
2021-12-28 14:17:18 -06:00
Ross Thompson
73af458eb5
More cleanup of dcache.
2021-12-28 14:12:18 -06:00
Ross Thompson
0e86e5d9f1
Additional cleanup of the LSU.
2021-12-28 13:59:07 -06:00
Ross Thompson
1e76c24f26
Major cleanup of the LSU.
2021-12-28 13:10:45 -06:00
Ross Thompson
79b17c5b55
Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
2021-12-28 12:33:07 -06:00
Ross Thompson
34c11ca8d5
Minor dcache cleanup.
2021-12-28 11:29:16 -06:00
Ross Thompson
243728d089
Moved all bus logic outside the dcache. Still needs cleanup.
2021-12-28 11:18:47 -06:00
Ross Thompson
74d636cb53
First cut at moving the dcache bus interface into the LSU.
...
Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
Ross Thompson
d366a1f50f
Moved dcache fetch logic outside the dcache except for the fsm.
2021-12-27 16:45:49 -06:00
Ross Thompson
e3ddcbb11e
Partial commit.
...
Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
2021-12-27 15:56:18 -06:00
David Harris
66ad7ddf1c
Added D and F tests to regression
2021-12-27 04:35:34 +00:00
David Harris
67d5b1bb42
Fixed exe2memfile.pl bug
2021-12-27 00:44:18 +00:00
David Harris
6e20d011d5
Fixed imperas C tests
2021-12-26 04:45:06 +00:00
David Harris
e6ed1372a7
Incorporated new Imperas tests. f and d tests are failing and c tests are hanging.
2021-12-26 04:36:53 +00:00
David Harris
48bb534658
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
d9e61fad67
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-25 06:37:30 -08:00
David Harris
9b491788b2
Checked in Chapter 2 C and assembly examples
2021-12-25 06:35:36 -08:00
Ross Thompson
d9977aa1f1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-23 12:40:42 -06:00
Ross Thompson
7fe70c3cc6
Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.
...
1: It simplifies the interactions between the caches and the hptw.
2: instruction page faults are fetched 3 times, caching them in the ITLB speeds up this process.
There are two downsides.
1: Pollute the TLBs with not very relavent translations
2: Have to compute the misalignment. This can be cached in the TLB which only costs 1 flip flop
for each TLB line.
2021-12-23 12:40:22 -06:00
Kip Macsai-Goren
ba7d116f10
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-22 15:41:12 +00:00
David Harris
a8c72c08a9
added wallyVirtIO.patch from Ross
2021-12-22 07:04:47 -08:00
Ross Thompson
4e1ae8c71f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-21 22:38:05 -06:00
Ross Thompson
f863bdc495
linux-wave.do changes.
2021-12-21 22:37:55 -06:00
