David Harris
4f1b0fdc64
Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
2022-05-08 06:46:35 +00:00
Ross Thompson
285fc6fd4d
Modified clint to support all byte write sizes.
2022-03-31 11:31:52 -05:00
Ross Thompson
fe896bff8e
Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
2022-03-24 23:47:28 -05:00
David Harris
2ea93c4ac3
adrdecs comments
2022-02-28 20:33:41 +00:00
David Harris
2de31a15da
Modified address decoder for native access to CLINT
2022-02-28 19:13:14 +00:00
David Harris
3a43450ac9
hptw cleanup for synthesis
2022-02-28 05:54:34 +00:00
Ross Thompson
ace743ae91
Changed HPTWRead/HPTWWrite to be HPTWRW to be similar to MemRW.
2022-02-21 16:54:38 -06:00
Ross Thompson
414e73edd9
Cleaned up names in lsuvirtmem.
2022-02-21 16:44:30 -06:00
Ross Thompson
456a54166a
Minor cleanup of lsu.
2022-02-21 12:46:06 -06:00
David Harris
4e194b2576
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-18 23:08:47 +00:00
David Harris
a88302f0d7
Removed problematic warning about reaching default state in HPTW
2022-02-18 23:08:40 +00:00
Ross Thompson
0bd533473c
New config option to enable hptw writes to PTE in memory to update Access and Dirty bits.
2022-02-17 17:19:41 -06:00
Ross Thompson
a7b774e453
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
d152733a17
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
Ross Thompson
4cfb601dc8
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
565ca4e4a3
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
David Harris
131a1a4ded
Cleaned warning on HPTW default state
2022-02-16 17:40:13 +00:00
David Harris
1326ade1a0
Removed depricated N-mode support and SI/EDELEG registers. rv64gc_wally64priv tests are failing, but seem to be failing before this change.
2022-02-15 19:20:41 +00:00
David Harris
de5e80696d
Cleaned up synthesis warnings
2022-02-11 01:15:16 +00:00
David Harris
38bbe23d14
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
Ross Thompson
862bf2faae
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
David Harris
6febce0001
Moved Dcache into bus block
2022-01-15 00:39:07 +00:00
Ross Thompson
66f3259984
Removed unused inputs to hptw.
2022-01-13 11:04:48 -06:00
David Harris
120fb7863f
Reformatted MIT license to 95 characters
2022-01-07 12:58:40 +00:00
Ross Thompson
c8d47fc7c3
Also fixed undetected bug with amo concurrent with tlb miss. It was possible for the amoalu to apply a function to the hptw readdata.
...
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-01-06 23:28:02 -06:00
Ross Thompson
0fddceffa6
Modified the mmu to not mux the lower 12 bits of the physical address and instead directly
...
assign from the input non translated virtual address. Since the lower bits never change there is
no reason to place these lower bits on a longer critical path.
The cache and lsu were previously using the lower bits from the virtual address rather than
the physical address. This change will allow us to keep the shorter critical path and
reduce the complexity of the lsu, ifu, and cache drawings.
2022-01-06 23:19:09 -06:00
David Harris
0e023e29d8
Code cleanup
2022-01-07 04:07:04 +00:00
David Harris
c9aa21d5a3
FPU debug and configurable logic cleanup
2022-01-06 18:10:25 +00:00
David Harris
c1d6550ccb
Removed generate statements
2022-01-05 14:35:25 +00:00
David Harris
b36ace221e
Renamed wally-pipelined to pipelined
2022-01-04 19:47:41 +00:00
