Ross Thompson
4d53b9002f
Broken.
...
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
5c2f774c35
Simplified tlbmixer mux to and-or
2021-07-08 23:34:24 -04:00
David Harris
74b6d13195
Fixed missing stall in InstrRet counter
2021-07-08 20:08:04 -04:00
David Harris
1190729896
TLB cleanup to match diagrams
2021-07-08 16:52:06 -04:00
Abe
b757c96b2d
Changed SvMode to SVMode on line 76
2021-07-06 23:28:58 -04:00
Kip Macsai-Goren
8350622f65
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-06 18:54:41 -04:00
David Harris
7d857cf4bd
more TLB name touchups
2021-07-06 18:39:30 -04:00
Kip Macsai-Goren
e08a578908
fixed upper bits page fault signal
2021-07-06 18:32:47 -04:00
David Harris
2e2aa2a972
connected signals in tlb by name instead of .*
2021-07-06 17:22:10 -04:00
David Harris
032c38b7e7
MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
2021-07-06 15:29:42 -04:00
David Harris
d58cad89a8
Replaced muxing of upper address bits with disregarding their match. Moved WriteEnables gate into tlblru to eliminate WriteLines
2021-07-06 10:38:30 -04:00
David Harris
694badcc6b
Created tlbcontrol module to hide details
2021-07-06 03:25:11 -04:00
