12 Commits

Author	SHA1	Message	Date
Domenico Ottolia	0c307d2db1	Fix synthesis warnings for privileged unit (replace 'initial' settings)	2021-04-20 17:57:56 -04:00
Domenico Ottolia	65abe13f4f	Cause an Illegal Instruction Exception when attempting to write readonly CSRs	2021-04-08 05:12:54 -04:00
Thomas Fleming	7126ab7864	Complete basic page table walker	2021-03-30 22:19:27 -04:00
Shreya Sanghai	1d6a2989ed	PC counts branch instructions	2021-03-23 14:25:51 -04:00
Shreya Sanghai	08e9149e20	made performance counters count branch misprediction	2021-03-16 11:24:17 -04:00
Thomas Fleming	7e11317a2d	Export SATP_REGW from csrs to MMU modules	2021-03-05 01:22:53 -05:00
David Harris	cf03afa880	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	c52a99ce2d	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	aad1d3d7dd	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00