10 Commits

Author	SHA1	Message	Date
David Harris	2543c29839	Initial (untested) implementation of lr and sc	2021-03-01 00:09:45 -05:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	d00d42cf9a	Merged bus into main	2021-02-25 00:28:41 -05:00
David Harris	8dec69c2ce	Added MUL	2021-02-15 22:27:35 -05:00
David Harris	3551cc859b	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	a44c2abb12	Minor tweaks	2021-02-02 19:44:37 -05:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	c23afbda3a	Moved LoadStall generation to IEU	2021-02-02 13:42:23 -05:00
David Harris	aad1d3d7dd	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00