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44196af61a
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163 Commits

Author SHA1 Message Date
Ross Thompson
44196af61a Have program which checks for sdc init and issues read, but read done is 
not correctly being read back by the software.  The error is in how the
sdc indicates busy.
 2021-09-24 15:53:38 -05:00
Ross Thompson
80e37d2291 Added SDC defines to each config mode. 
Added sd_top which is the sd card reader.
 2021-09-24 12:24:30 -05:00
Ross Thompson
fea439b84d SDC to ABHLite interface partially done. 
Added SDC to adrdec and uncore.
 2021-09-24 10:45:09 -05:00
David Harris
9ae25b0cea Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression. 2021-09-15 13:14:00 -04:00
Ross Thompson
570aab4275 Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches. 2021-09-11 15:40:27 -05:00
Ross Thompson
86fbe2a654 Changed configs to support 4 ways set associative caches. 2021-09-08 12:52:49 -05:00
Ross Thompson
6550f38af9 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-09-08 12:47:03 -05:00
Ross Thompson
49e75d579c Set associate icache working, but way 0 is never written. 2021-09-07 12:46:16 -05:00
Katherine Parry
70f332fe2f FMA cleanup 2021-08-28 10:53:35 -04:00
Katherine Parry
aedd71d570 move some FPU select muxs to execute stage 2021-08-13 14:41:22 -04:00
Katherine Parry
e00f181bcf LZA added to FMA and attemting a merged FMA and adder in synthesis 2021-08-10 13:57:16 -04:00
Ross Thompson
c749d08542 fixed the read timer issue but we still have problems with interrupts and i/o devices. 2021-08-06 10:16:06 -05:00
Katherine Parry
ef28679721 fpu cleanup 2021-07-24 14:59:57 -04:00
bbracker
d3059dd04c fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
Katherine Parry
b9081e514c FMA parameterized 2021-07-20 22:04:21 -04:00
David Harris
1f3dfa20f6 flag for optional boottim 2021-07-20 14:46:37 -04:00
David Harris
e1a1a8395e Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
Ross Thompson
508c3e35af Restored TIM range. 2021-07-19 21:17:31 -05:00
David Harris
4d40b5faef Added cache configuration to config files 2021-07-19 18:19:46 -04:00
David Harris
46ab609498 Updated FMA1 with parameterized size 2021-07-18 20:40:49 -04:00
David Harris
4f8f52f283 Added FLEN, NE, NF to config and started using these in FMA1 2021-07-18 17:28:25 -04:00
David Harris
8d348dacce Started atomics 2021-07-17 21:11:41 -04:00
David Harris
1bd5c137a6 Reduced size of physical memory by 16 for performance 2021-07-16 20:10:12 -04:00
Ross Thompson
6521d2b468 Also changed the shadow ram's dcache copy widths. 
Merge branch 'dcache' into main
 2021-07-16 14:21:09 -05:00
Ross Thompson
1aabee0478 Updated the config so the tim has a bigger range. 2021-07-16 12:35:00 -05:00
Katherine Parry
c74d26eea4 Fixed lint warning 2021-07-14 21:24:48 -04:00
Katherine Parry
efdec72df1 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
Katherine Parry
36f59f3c99 Almost all convert instructions pass Imperas tests 2021-07-11 18:06:33 -04:00
Abe
84711fbdc8 Updated MISA defining as well as porting sizes for peripherals (34 to 56) 2021-07-07 02:37:09 -04:00
David Harris
71711c54c9 Don't generate HPTW when MEM_VIRTMEM=0 2021-07-05 23:35:44 -04:00
David Harris
6bac566bb7 Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0 2021-07-05 20:35:31 -04:00
David Harris
80666f0a71 Added ASID & Global PTE handling to TLB CAM 2021-07-04 17:52:00 -04:00
David Harris
ccd9c05303 Switched to array notation for pmpchecker 2021-07-04 10:51:56 -04:00
David Harris
9645b023c9 Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang. 2021-07-04 01:19:38 -04:00
Ross Thompson
7b3716c281 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-02 13:56:49 -05:00
Ross Thompson
dbd33465e1 Merge branch 'main' into bigbadbranch 2021-07-02 11:52:26 -05:00
David Harris
76a43eb468 Optimized PMP checker logic and added support for configurable number of PMP registers 2021-07-02 11:05:25 -04:00
Ross Thompson
d6c19e73f4 Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults. 2021-06-25 11:05:17 -05:00
Kip Macsai-Goren
d7e518991e Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR. 2021-06-24 20:01:11 -04:00
Ross Thompson
aeeaf6d919 Progress. 2021-06-24 13:05:22 -05:00
David Harris
d2ec04564b Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals 2021-06-20 22:59:04 -04:00
bbracker
23f479d225 remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR 2021-06-20 22:38:25 -04:00
Katherine Parry
2b67f25683 all rv64f instructions except convert, divide, square root, and FLD pass 2021-06-20 20:24:09 -04:00
bbracker
83a0a37f8e make xCOUNTEREN what buildroot expects it to be 2021-06-20 09:22:31 -04:00
bbracker
a3eafc6e5b change buildroot config to use relative path for testvectors 2021-06-18 22:28:07 -04:00
Abe
a0a4b09c94 Updated directory coremark_bare's wally-config file to define PMP_ENTRIES 2021-06-18 11:46:25 -04:00
David Harris
35c74348a4 allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
David Harris
679e507cc6 Added SUPPORTED to each peripheral in each config file 2021-06-17 21:36:32 -04:00
David Harris
da8eb7749f Started simplifying PMA checker 2021-06-17 16:28:06 -04:00
Katherine Parry
4177f4f148 Updated FMA 2021-06-14 13:42:53 -04:00