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Author SHA1 Message Date
Kip Macsai-Goren
41ef59ddfe Removed Sail from virt mem tests due to sail not recognizing SVADU 2023-04-11 17:41:31 -07:00
Kip Macsai-Goren
4bf2a7e15b Added sail simulation to priv tests that support it 2023-04-11 13:26:59 -07:00
David Harris
4797f6ca5e
Merge pull request #230 from ACWright256/main 
Excluded coverage for misaligned instructions
 2023-04-11 05:21:09 -07:00
Alexa Wright
34fd402f23 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
David Harris
a819a24b83
Merge pull request #226 from SydRiley/main 
Increased coverage for the fpu by adding directed tests to toggle signals
 2023-04-09 21:52:11 -07:00
David Harris
df96732683
Merge pull request #223 from ross144/main 
Solves issue 172
 2023-04-09 20:30:26 -07:00
David Harris
2e97aa46db
Merge pull request #224 from kbox13/my-single-change 
Create new PMP tests
 2023-04-09 20:29:03 -07:00
Kevin Box
f74bb8b38e Create new pmp tests 
configures all pmpcfg registers in each different address range.
 2023-04-09 16:29:57 -07:00
Sydeny
ff405a49a5 Increasing coverage for the fpu by adding directed tests to toggle signals 2023-04-09 13:33:12 -07:00
Ross Thompson
d67ee33896 Updated wally figure again to increase resolution. 2023-04-09 12:26:15 -05:00
Ross Thompson
f6c84b1e8d Updated wally top level figure to fix issue 172. 2023-04-09 12:20:43 -05:00
Ross Thompson
132016f131 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-09 12:19:44 -05:00
David Harris
11cadb3f8f
Merge pull request #222 from kjprime/main 
Remove unnecessary check from compressed instruction decode
 2023-04-09 04:56:21 -07:00
David Harris
c8cd2ffc77
Merge pull request #221 from dherreravicioso/main 
Added test coverage for Privilege Unit in CSRs
 2023-04-09 04:54:36 -07:00
Kevin Thomas
640310cf94 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-08 22:56:20 -05:00
Diego Herrera Vicioso
76d5c3e500 Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs. 2023-04-08 16:40:36 -07:00
Ross Thompson
e79119e2fd
Merge pull request #220 from davidharrishmc/dev 
Obscure coverage fixes
 2023-04-08 10:27:31 -05:00
David Harris
d27779f4c0 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-07 21:57:18 -07:00
David Harris
4a2f641348 Waived coverage on BTB memory with byte write enables tied high 2023-04-07 21:56:49 -07:00
David Harris
495f2ed274 Improved RAS predictor coverage by eliminating unreachable StallM term 2023-04-07 21:37:12 -07:00
Ross Thompson
a36a8ef6f5
Merge pull request #219 from davidharrishmc/dev 
Spill logic coverage and fdivsqrt cleanup
 2023-04-07 23:30:52 -05:00
David Harris
5119222c2f Commented WFI non-flush in writeback stage of hazard unit 2023-04-07 21:27:13 -07:00
David Harris
a9b7bd101e Added vm64check tests to cover IMMU vm64 2023-04-07 21:14:52 -07:00
David Harris
25f394ce97 Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf 2023-04-07 21:11:01 -07:00
David Harris
5c6d9f87a0 Fixed priv.S to initialize stimecmp and agree with ImperasDV 2023-04-07 20:44:01 -07:00
David Harris
7ad8d7f774 Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
David Harris
8b4016582b Fixed WALLY-init-lib to return correctly even from traps from compressed instructions 2023-04-07 20:24:33 -07:00
David Harris
982ade31c5 Fixed enabling machine timer interrupt 2023-04-06 22:18:33 -07:00
David Harris
c9887cb182 vm64 tests 2023-04-06 21:42:47 -07:00
David Harris
c24e81c57f Division cleanup 2023-04-06 21:42:34 -07:00
David Harris
ce931d1fc5 Simplified integer division preprocessing in fdivsqrt 2023-04-06 16:43:28 -07:00
David Harris
f810ad3cec Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-06 14:07:59 -07:00
David Harris
1569bfbb98 Removed redundant stall signal to get spill coverage 2023-04-06 14:07:50 -07:00
Ross Thompson
87a1d12c3b Merge branch 'main' of github.com:ross144/cvw 2023-04-06 15:33:24 -05:00
Ross Thompson
b57566e632 Added Jacob's ILA script. 2023-04-06 15:32:36 -05:00
Ross Thompson
fe922c8fac Fixed syntax error. 2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1 Added note about strange vivado behavior not inferring block ram. 2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997 Similifed the no byte write enabled version of the sram model. 2023-04-06 14:18:41 -05:00
Kevin Thomas
1931859c45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-06 12:38:41 -05:00
David Harris
fddbd79209
Update dvtestplan.md 2023-04-06 09:29:47 -07:00
David Harris
6431e358ca
Create dvtestplan.md 2023-04-06 09:23:09 -07:00
David Harris
4448c238c4
Merge pull request #214 from eroom1966/main 
Add in configuration for B extension
 2023-04-06 09:08:20 -07:00
Lee Moore
a20528e43c
Merge branch 'openhwgroup:main' into main 2023-04-06 16:31:49 +01:00
eroom1966
430763a1d1 add support into configuration for Zb(a,b,c,s) 2023-04-06 16:30:14 +01:00
David Harris
2a3711546f
Merge pull request #213 from eroom1966/main 
fix break to simulation testbench
 2023-04-06 06:54:59 -07:00
eroom1966
319a1b9161 fix break to simulation testbench 2023-04-06 14:45:41 +01:00
David Harris
52dcd63d1e
Merge pull request #211 from ross144/main 
Fixes the issue introduced by the fix for issue 203
 2023-04-05 21:50:32 -07:00
Ross Thompson
1478115faf Fixed wally64/32priv test hangup. 
The fix for the issue 203 had a lingering bug which did not suppress a bus access if the hptw short circuits on a pma/p fault.
 2023-04-05 23:13:45 -05:00
Kevin Thomas
5d71960385 Merge branch 'main' of https://github.com/kjprime/cvw 2023-04-05 17:44:54 -05:00
Kevin Thomas
0b317c4823
Merge branch 'openhwgroup:main' into main 2023-04-05 17:44:47 -05:00