Ross Thompson
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38160fe6ea
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-03 17:56:55 -05:00 |
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David Harris
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fb95767da0
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Fixed bug with CSRRS/CSRRC for MIP/SIP
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2022-04-03 20:18:25 +00:00 |
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Ross Thompson
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3db60a1cc1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-02 16:39:54 -05:00 |
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Ross Thompson
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2376d66ec2
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Added more ILA signals.
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2022-04-02 16:39:45 -05:00 |
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Kip Macsai-Goren
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37c755e6ce
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added RV64IA config to have a config without compressed instructions
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2022-04-02 18:24:08 +00:00 |
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Ross Thompson
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691f1a6b0d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 17:18:25 -05:00 |
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Ross Thompson
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51dfa16f59
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Updated the fpga test bench.
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2022-04-01 17:14:47 -05:00 |
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Ross Thompson
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48c49802b2
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Fixed linting issues.
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2022-04-01 15:20:45 -05:00 |
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Ross Thompson
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301f20052b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-01 12:50:34 -05:00 |
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Ross Thompson
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19a8df9739
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Added wave config
added new signals to ILA.
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2022-04-01 12:44:14 -05:00 |
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bbracker
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9d26bfe71d
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expand WALLY-PERIPH test to use SEIP on PLIC context 1
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2022-03-31 18:02:06 -07:00 |
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bbracker
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e09079d8b4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 17:54:43 -07:00 |
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bbracker
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55df8bc3f7
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fix lingering overrun error bug
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2022-03-31 17:54:32 -07:00 |
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Ross Thompson
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48c862d536
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Added PLIC to ILA.
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2022-03-31 16:44:49 -05:00 |
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Ross Thompson
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da93d14050
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 16:30:55 -05:00 |
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Ross Thompson
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b5cdf035fc
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 15:50:04 -05:00 |
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Ross Thompson
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ade4a4cd5e
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Notes on what to change in ram.sv.
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2022-03-31 15:48:15 -05:00 |
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bbracker
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bdb3417656
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 13:46:32 -07:00 |
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bbracker
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0f7e995055
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simplify plic logic
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2022-03-31 13:46:24 -07:00 |
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David Harris
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c7043e4d63
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Added SystemVerilog flag to fma.do so that fma16 compiles properly
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2022-03-31 17:00:38 +00:00 |
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Ross Thompson
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88c5cdc873
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 11:39:41 -05:00 |
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Ross Thompson
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bf9683f0d2
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Forced to go back to hard coded preload.
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2022-03-31 11:39:37 -05:00 |
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Ross Thompson
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54001222cf
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-31 11:38:55 -05:00 |
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Ross Thompson
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285fc6fd4d
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Modified clint to support all byte write sizes.
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2022-03-31 11:31:52 -05:00 |
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David Harris
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dd3af17b3f
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Added synthesis script for fma16
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2022-03-31 00:51:33 +00:00 |
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David Harris
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3457c6e512
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-30 23:06:36 +00:00 |
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bbracker
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69a0f6e00b
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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Ross Thompson
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0a5b500aca
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Changed sram1p1rw to have the same type of bytewrite enables as bram.
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2022-03-30 11:38:25 -05:00 |
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David Harris
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9b1f85d353
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-30 16:26:27 +00:00 |
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David Harris
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08fad856e3
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-30 16:13:42 +00:00 |
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Ross Thompson
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e4f4e1bd43
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-30 11:09:44 -05:00 |
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Ross Thompson
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f52ab01362
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Partial cleanup of memories.
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2022-03-30 11:09:21 -05:00 |
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Ross Thompson
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839bede656
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Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.
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2022-03-30 11:04:15 -05:00 |
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Ross Thompson
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997c1b87fe
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rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.
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2022-03-29 23:48:19 -05:00 |
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Ross Thompson
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66e9380cfb
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Partial fix to allow byte write enables with fpga and still get a preload to work.
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2022-03-29 19:12:29 -05:00 |
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Kip Macsai-Goren
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d031c003ba
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fixed arch bge test signature output location after update
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2022-03-29 20:45:18 +00:00 |
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David Harris
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03fa9084bc
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Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv
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2022-03-29 19:16:41 +00:00 |
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David Harris
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c4f2c6b110
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fpu compare simplification, minor cleanup
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2022-03-29 17:11:28 +00:00 |
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Kip Macsai-Goren
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56a0542405
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made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes
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2022-03-29 02:26:42 +00:00 |
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Kip Macsai-Goren
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a6d90a25c2
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fixed signature location of the new periph with no compressed instructions
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2022-03-29 02:15:17 +00:00 |
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bbracker
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8ea25e591b
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fix typo that Madeleine found
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2022-03-28 15:39:29 -07:00 |
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Kip Macsai-Goren
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709f8e6e0d
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fixed double multiplication on vectored interrupts
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2022-03-28 19:12:31 +00:00 |
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Kip Macsai-Goren
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eb337fd3e1
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added test config that doesn't use compressed instructions for privileged tests
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2022-03-28 19:12:31 +00:00 |
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Skylar Litz
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f91fb7a388
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add AtemptedInstructionCount signal
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2022-03-26 21:28:57 +00:00 |
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Skylar Litz
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62a330c290
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update to match new filesystem organization
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2022-03-26 21:28:32 +00:00 |
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Kip Macsai-Goren
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7ae1d14191
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added basic trap tests that do not pass regression yet. updated signature adresses
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2022-03-25 22:57:41 +00:00 |
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Ross Thompson
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61c714ebe6
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I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.
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2022-03-25 13:10:31 -05:00 |
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Ross Thompson
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fe896bff8e
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Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.
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2022-03-24 23:47:28 -05:00 |
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bbracker
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6f6663cd67
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fix multiple-context PLIC checkpoint generation
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2022-03-25 01:02:22 +00:00 |
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bbracker
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d33de3ef6b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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