Ross Thompson
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a99c0502e5
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Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
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2021-03-24 15:56:55 -05:00 |
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Shreya Sanghai
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1d6a2989ed
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PC counts branch instructions
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2021-03-23 14:25:51 -04:00 |
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Shreya Sanghai
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bbe0957df5
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
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2021-03-18 17:25:48 -04:00 |
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Thomas Fleming
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7f7597e667
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Connect tlb, pagetablewalker, and memory
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2021-03-18 14:35:46 -04:00 |
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Shreya Sanghai
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08e9149e20
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made performance counters count branch misprediction
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2021-03-16 11:24:17 -04:00 |
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Thomas Fleming
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7e11317a2d
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Export SATP_REGW from csrs to MMU modules
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2021-03-05 01:22:53 -05:00 |
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David Harris
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cf03afa880
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Eliminated flushing pipeline on CSR reads
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2021-02-26 17:00:07 -05:00 |
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David Harris
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37dba8fd26
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More memory interface, ALU testgen
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2021-02-15 10:10:50 -05:00 |
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David Harris
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d56d7a75a6
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Rename ifu/dmem/ebu signals to match uarch diagram
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2021-02-02 15:09:24 -05:00 |
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David Harris
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aad1d3d7dd
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Moved writeback pipeline registers from datapth into DMEM and CSR
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2021-02-02 13:02:31 -05:00 |
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David Harris
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9d7e242596
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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396cea1ea7
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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