Ross Thompson
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d11136c406
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Fixed bug with the external memory region selection.
Updated bios program to copy just 127MB to dram.
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2021-10-19 11:23:23 -05:00 |
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Ross Thompson
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af53657eaf
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Merge branch 'sdc' into fpga
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2021-09-25 19:33:07 -05:00 |
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Ross Thompson
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86524a5f64
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Now have software interacting with the initialization and settting the address register.
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2021-09-24 18:30:26 -05:00 |
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Ross Thompson
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c644e940c2
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Updated Imperas test bench to work with the SDC reader.
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2021-09-24 11:22:54 -05:00 |
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Ross Thompson
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fea439b84d
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SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
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2021-09-24 10:45:09 -05:00 |
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Ross Thompson
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a7be88a43b
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Changes to make fpga synthesizable.
Added preload to test simple program on wally in fpga.
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2021-09-22 10:54:13 -05:00 |
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Ross Thompson
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af74a8c5cb
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Third attempt at fixing the write enables for the icache cacheway.
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2021-09-09 15:49:27 -05:00 |
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bbracker
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f9b6bd91f5
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fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk
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2021-07-20 17:55:44 -04:00 |
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David Harris
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1f3dfa20f6
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flag for optional boottim
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2021-07-20 14:46:37 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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David Harris
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1fa4abf7b6
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Changed IMMU ExecuteAccessF to 1 rather than InstrReadF to fix buildroot; simplified PMP checker
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2021-07-03 03:29:33 -04:00 |
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Kip Macsai-Goren
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d7e518991e
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Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
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2021-06-24 20:01:11 -04:00 |
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David Harris
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fa51ab9f68
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Refactored pmachecker to have adrdecs used in uncore
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2021-06-23 01:41:00 -04:00 |
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bbracker
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303f8e2a7f
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give EBU a dedicated PMA unit as just an address decoder
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2021-06-22 18:28:08 -04:00 |
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David Harris
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d2ec04564b
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Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
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2021-06-20 22:59:04 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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336936cc39
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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5a661a7392
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provide time and timeh CSRs based on CLINT's counter
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2021-06-17 08:38:30 -04:00 |
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Thomas Fleming
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38236e9172
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Implement first pass at the PMA checker
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2021-04-22 15:34:02 -04:00 |
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bbracker
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368c94d4ff
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working GPIO interrupt demo
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2021-04-15 21:09:15 -04:00 |
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bbracker
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31c6b2d01f
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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bbracker
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11d4a8ab34
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first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
|
Noah Boorstin
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a2b0af460e
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everyone gets a bootram
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2021-03-18 12:35:37 -04:00 |
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bbracker
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850a2e9329
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added a delay to sel signals
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2021-03-05 15:07:34 -05:00 |
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bbracker
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77e2e357a7
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more merging fixes
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2021-03-05 14:36:07 -05:00 |
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bbracker
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ed4ff1ecd0
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remove deprecated mem signals
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2021-03-05 14:27:38 -05:00 |
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bbracker
|
0f4a231543
|
first merge of ahb fix
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2021-03-05 14:24:22 -05:00 |
|
Noah Boorstin
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dfae278ffb
|
busybear: make imperas tests work again
|
2021-03-04 22:44:49 +00:00 |
|
Noah Boorstin
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4833b36535
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busybear: more adapting to new memory system
|
2021-03-01 18:50:42 +00:00 |
|
Noah Boorstin
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6e70ae8b3d
|
busybear: add 2nd dtim for bootram
|
2021-02-28 16:08:54 +00:00 |
|
Noah Boorstin
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edd5e9106d
|
busybear: remove gpio, start adding 2nd ram
|
2021-02-28 06:02:40 +00:00 |
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David Harris
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d00d42cf9a
|
Merged bus into main
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2021-02-25 00:28:41 -05:00 |
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bbracker
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9231646fb3
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bus rw bugfix and peripherals testing
|
2021-02-12 00:02:45 -05:00 |
|
David Harris
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3551cc859b
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Data memory bus integration
|
2021-02-07 23:21:55 -05:00 |
|
David Harris
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9d7e242596
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
|
David Harris
|
396cea1ea7
|
Reorganized src hierarchically
|
2021-01-30 11:50:37 -05:00 |
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