David Harris
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80666f0a71
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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9645b023c9
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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David Harris
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35c74348a4
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allow all size memory access in CLINT; added underscore to peripheral address symbols
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2021-06-18 08:05:50 -04:00 |
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David Harris
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679e507cc6
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Added SUPPORTED to each peripheral in each config file
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2021-06-17 21:36:32 -04:00 |
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David Harris
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0ffbd03139
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More verilator fixes, but bpred is broken
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2021-06-09 21:03:03 -04:00 |
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Kip Macsai-Goren
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a95a7a7b82
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working version with new mmu comments, old boottim values
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2021-06-08 15:20:25 -04:00 |
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David Harris
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b613f46c2d
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Resized BOOT TIM to 1 KB
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2021-06-08 14:04:32 -04:00 |
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David Harris
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2ae5ca19b5
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Continued merge
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2021-06-07 12:49:47 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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David Harris
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dc0b19dfaa
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Merge difficulties
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2021-06-07 09:50:23 -04:00 |
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David Harris
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d5ec797ba4
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Refactored configuration files and renamed testbench-busybear to testbench-linux
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2021-06-07 09:46:52 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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David Harris
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a26bf37be8
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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Ross Thompson
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72363f5c66
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Added the ability to exclude branch predictor.
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2021-04-26 14:27:42 -05:00 |
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Ross Thompson
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6e803b724e
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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Noah Boorstin
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6954e6df4c
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buildroot: sim is now running!
yes it only gets through 5 instructions right now. Yes that's my fault.
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2021-04-17 14:44:32 -04:00 |
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bbracker
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31c6b2d01f
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Yee hoo first draft of PLIC plus self-checking tests
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2021-04-04 06:40:53 -04:00 |
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Ross Thompson
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e1842c8da6
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Broken commit. Trying to get exe2memfile.pl to work correctly with non 0x8000_0000 starting addresses.
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2021-03-23 13:54:59 -05:00 |
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bbracker
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11d4a8ab34
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first pass at PLIC interface
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2021-03-22 10:14:21 -04:00 |
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Shreya Sanghai
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bbe0957df5
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
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2021-03-18 17:25:48 -04:00 |
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Ross Thompson
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1091dd10c1
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Switched to gshare from global history.
Fixed a few minor bugs.
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2021-03-18 16:05:59 -05:00 |
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Noah Boorstin
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bc1a0c6ee7
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change ifndef to generate/if
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2021-03-18 12:50:19 -04:00 |
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Noah Boorstin
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a2b0af460e
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everyone gets a bootram
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2021-03-18 12:35:37 -04:00 |
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Elizabeth Hedenberg
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da758e9e14
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Merge branch '3_3_2021' into main
Making sure coremark works with spring break changes
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2021-03-17 14:11:37 -04:00 |
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Shreya Sanghai
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36f0631203
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added gshare and global history predictor
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2021-03-16 17:03:01 -04:00 |
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Shreya Sanghai
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9eed875886
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added global history branch predictor
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2021-03-16 16:06:40 -04:00 |
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Shreya Sanghai
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74f1641c5a
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Merge branch 'counters' into main
added a configurable number of performance counters
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2021-03-16 11:01:30 -04:00 |
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Ross Thompson
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4c8952de6a
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Converted branch predictor preloads to use system verilog rather than modelsim's load command.
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2021-03-15 12:39:44 -05:00 |
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Shreya Sanghai
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f0ec365117
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added performance counters
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2021-03-04 11:42:52 -05:00 |
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Teo Ene
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6ebb79abe0
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Linux CoreMark is operational
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2021-03-04 05:58:18 -06:00 |
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Teo Ene
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08a7f6ec25
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In the process of updating coremark.RV64I program to work with Dr. Harris's perl script. Commiting to make it easier to switch branches
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2021-03-04 01:27:05 -06:00 |
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Teo Ene
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61b872a3e8
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Changed TIMBASE in coremark config file
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2021-02-25 11:03:41 -06:00 |
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Teo Ene
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3e5de35fc4
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Added provisional coremark files from work with Elizabeth
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2021-02-24 20:07:07 -06:00 |
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