Ross Thompson
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b6d75d453a
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Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
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2021-12-20 10:03:56 -06:00 |
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Ross Thompson
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beb1988539
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-20 10:03:19 -06:00 |
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Ross Thompson
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df8bd78679
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More signal name cleanup in LSU.
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2021-12-19 22:47:48 -06:00 |
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Ross Thompson
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3eb5f33705
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Remove verbosity from lsu state machine.
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2021-12-19 22:41:34 -06:00 |
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Ross Thompson
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d3c3422d12
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Rename of SelPTW to SelHPTW.
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2021-12-19 22:24:07 -06:00 |
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Ross Thompson
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8feb36b926
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Signal renames.
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2021-12-19 22:21:03 -06:00 |
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Ross Thompson
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dc82d44f9e
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Hardware reductions in the lsu.
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2021-12-19 22:00:28 -06:00 |
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Ross Thompson
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dc95896303
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Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent.
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2021-12-19 21:36:54 -06:00 |
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Ross Thompson
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138da1fefa
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Removed lsuArb and placed remaining logic in lsu.sv.
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
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2021-12-19 21:34:40 -06:00 |
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Ross Thompson
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cc5c5da8bc
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Added file showing how to compile riscv toolchain for different extension combinations.
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2021-12-19 20:31:55 -06:00 |
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Ross Thompson
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596cc4fde4
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Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card.
mv qemu patches to tests directory.
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2021-12-19 20:11:32 -06:00 |
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David Harris
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a25d541dcf
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Moved generate of conditional units to hart
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2021-12-19 17:03:57 -08:00 |
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David Harris
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3c3bfd055e
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Moved generate statements for optional units into wallypipelinedhart
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2021-12-19 16:53:41 -08:00 |
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Ross Thompson
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d9cc9afd49
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Changes to buildroot to support MemAdrM to IEUAdrM name changes.
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2021-12-19 18:24:40 -06:00 |
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Ross Thompson
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32a4afc7a1
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-19 18:16:49 -06:00 |
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Ross Thompson
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a39b47d226
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Switched to using an always block for lsu stall logic. This avoids the problematic x propagation.
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2021-12-19 18:16:08 -06:00 |
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Ross Thompson
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eceb418056
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Implemented what I think is the last required change for the lsu state machine.
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2021-12-19 17:57:12 -06:00 |
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Ross Thompson
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fe5c05eb8d
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Created hack to get around imperas64mmu unknown (value = x) bug.
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2021-12-19 17:53:13 -06:00 |
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Ross Thompson
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c453b285dc
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Fixed bug where icache did not replay PCF on itlb miss.
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2021-12-19 17:01:13 -06:00 |
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Ross Thompson
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c9291655da
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Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
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2021-12-19 16:12:31 -06:00 |
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David Harris
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53cd2ac049
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-19 13:53:53 -08:00 |
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David Harris
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9e6c9c38c0
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ALUControl cleanup
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2021-12-19 13:53:45 -08:00 |
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Katherine Parry
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e3f2a252cd
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fixed some small errors in FMA
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2021-12-19 13:51:46 -08:00 |
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Ross Thompson
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f4d778c2f6
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Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
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2021-12-19 15:10:33 -06:00 |
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Ross Thompson
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a445bedcd2
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Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
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2021-12-19 14:57:42 -06:00 |
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Ross Thompson
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225cd5a114
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Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
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2021-12-19 14:00:30 -06:00 |
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Ross Thompson
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cd3c1032b7
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Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
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2021-12-19 13:55:57 -06:00 |
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Ross Thompson
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1126135b80
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minro change. comments about needed changes in dcache.
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2021-12-19 13:53:02 -06:00 |
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David Harris
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f201af4bb7
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Renamed zero to eq in flag generation
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2021-12-19 11:49:15 -08:00 |
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David Harris
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406f129bed
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Controller fix
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2021-12-18 22:08:23 -08:00 |
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David Harris
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67577d7c91
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Renamed RD1D to R1D, etc.
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2021-12-18 21:26:00 -08:00 |
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David Harris
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721d0b5bcf
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Simplified shifter right input
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2021-12-18 10:25:40 -08:00 |
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Ross Thompson
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4daeb6657f
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Merge branch 'tlb_fixes' into main
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2021-12-18 12:24:17 -06:00 |
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David Harris
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7e026f3e78
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Simplified Shifter Right input
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2021-12-18 10:21:17 -08:00 |
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David Harris
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27ec8ff893
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Shared ALU mux input for shifts
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2021-12-18 10:08:52 -08:00 |
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David Harris
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eed2765033
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Factored out common parts of shifter
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2021-12-18 10:01:12 -08:00 |
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David Harris
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53baf3e787
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Cleaning shifter
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2021-12-18 09:43:09 -08:00 |
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David Harris
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ebcffcdebd
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Moved W64 truncation after result mux
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2021-12-18 09:27:25 -08:00 |
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David Harris
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23c6b6370f
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Forwarding logic factoring
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2021-12-18 05:40:38 -08:00 |
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David Harris
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10dfefa8ad
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Simplified FWriteInt interfaces by merging into RegWrite
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2021-12-18 05:36:32 -08:00 |
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David Harris
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0f319b45c1
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Do File cleanups
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2021-12-17 17:45:26 -08:00 |
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Ross Thompson
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bbd1332353
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Merge remote-tracking branch 'origin/tlb_fixes' into main
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2021-12-17 14:40:29 -06:00 |
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Ross Thompson
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a11597b6bd
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Added more debugging code for FPGA.
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2021-12-17 14:40:25 -06:00 |
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Ross Thompson
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ee81cfff0c
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Possible fix for icache deadlock interaction with hptw.
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2021-12-17 14:38:25 -06:00 |
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David Harris
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d9f569afe1
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Added irscv-arch-test and rsicv-isa-sim
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2021-12-15 12:38:35 -08:00 |
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David Harris
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aebd746e71
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Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
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2021-12-15 12:10:45 -08:00 |
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David Harris
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4e35736e90
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IEU cleanup:
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2021-12-15 11:38:26 -08:00 |
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Ross Thompson
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6d2a4b8354
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Oups missed files in the last commit.
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2021-12-15 10:25:08 -06:00 |
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Ross Thompson
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21b13fc237
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Reverted 23Mhz to 10Mhz. The flash card can't work at that speed.
added icache debugging signals.
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2021-12-15 10:24:29 -06:00 |
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David Harris
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865d5ce0b1
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Renamed dtim->ram and boottim ->bootrom
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2021-12-14 13:43:06 -08:00 |
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