Noah Limpert
15bdf5680e
removed .* instantiation from ieu.sv and datapth.sv in ieu folder
2021-12-08 00:24:27 -08:00
Kip Macsai-Goren
7a8c21e71f
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
David Harris
d24bece3a8
Lint cleanup
2021-10-23 09:58:52 -07:00
Ross Thompson
551e3491af
Moved the ReadDataW register into the datapath.
...
The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
ec80cc1820
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
...
Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
David Harris
b23192cf1b
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
Katherine Parry
0c2b7a1132
FPU control signals changed and FMA works
2021-06-28 18:53:58 -04:00
bbracker
34dbad967d
ah merge; I checked and this does pass all of regression except lints
2021-06-25 07:37:06 -04:00
Katherine Parry
7e3483b283
FPU forwarding reworked pt.1
2021-06-24 18:39:18 -04:00
bbracker
2155a4e485
Revert "fixed forwarding"
...
This reverts commit 86e369df52
2021-06-24 17:39:37 -04:00
bbracker
86e369df52
fixed forwarding
2021-06-24 11:20:21 -04:00
Katherine Parry
90d5fdba04
FMV.X.D imperas test passes
2021-05-24 14:44:30 -04:00
Katherine Parry
06af239e6c
FMV.D.X imperas test passes
2021-05-20 22:17:59 -04:00
Ross Thompson
a99c0502e5
Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
2021-03-24 15:56:55 -05:00
Shreya Sanghai
eb86bfc084
removed unnecesary PC registers in ifu
2021-03-18 16:31:21 -04:00
Ross Thompson
66e84f3a2c
Merge branch 'bp' into main
...
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
David Harris
2543c29839
Initial (untested) implementation of lr and sc
2021-03-01 00:09:45 -05:00
Ross Thompson
7592a0dacb
Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
2021-02-26 20:12:27 -06:00
David Harris
015b632eb1
Cleaned out unused signals
2021-02-26 09:17:36 -05:00
David Harris
d00d42cf9a
Merged bus into main
2021-02-25 00:28:41 -05:00
David Harris
8dec69c2ce
Added MUL
2021-02-15 22:27:35 -05:00
David Harris
3551cc859b
Data memory bus integration
2021-02-07 23:21:55 -05:00
David Harris
a44c2abb12
Minor tweaks
2021-02-02 19:44:37 -05:00
David Harris
d56d7a75a6
Rename ifu/dmem/ebu signals to match uarch diagram
2021-02-02 15:09:24 -05:00
David Harris
c23afbda3a
Moved LoadStall generation to IEU
2021-02-02 13:42:23 -05:00
David Harris
aad1d3d7dd
Moved writeback pipeline registers from datapth into DMEM and CSR
2021-02-02 13:02:31 -05:00
David Harris
396cea1ea7
Reorganized src hierarchically
2021-01-30 11:50:37 -05:00
