15 Commits

Author	SHA1	Message	Date
Noah Boorstin	f48af209c4	busybear: make CSRs only weird for us	2021-03-05 00:46:32 +00:00
Noah Boorstin	bcc0010498	Merge branch 'main' into busybear	2021-02-28 20:45:08 +00:00
Noah Boorstin	a03796a519	busybear: change sstatus, mstatus reset value	2021-02-28 16:19:03 +00:00
David Harris	cf03afa880	Eliminated flushing pipeline on CSR reads	2021-02-26 17:00:07 -05:00
David Harris	015b632eb1	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
kaveh pezeshki	c7863d58cd	merged with main to integrate with AHB	2021-02-26 05:37:10 -08:00
David Harris	c52a99ce2d	Fixed fetch stall after jump in bus unit	2021-02-23 09:08:57 -05:00
Noah Boorstin	5835641c6c	busybear testbench: check (almost) all the CSRs	2021-02-16 20:03:24 -05:00
David Harris	37dba8fd26	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
Noah Boorstin	14cde0d59c	Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.	2021-02-04 22:03:45 +00:00
David Harris	a44c2abb12	Minor tweaks	2021-02-02 19:44:37 -05:00
David Harris	d56d7a75a6	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	aad1d3d7dd	Moved writeback pipeline registers from datapth into DMEM and CSR	2021-02-02 13:02:31 -05:00
David Harris	9d7e242596	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	396cea1ea7	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00