14 Commits

Author	SHA1	Message	Date
David Harris	f8ad1b3db8	Improved IEU and bitmanip test coverage	2023-03-23 14:24:41 -07:00
David Harris	081a817925	Merge pull request #98 from ross144/main ... New gshare implementation	2023-02-20 11:27:47 -08:00
David Harris	df9950483e	Removed unused and incomplete ROM macro instantations	2023-02-20 05:59:57 -08:00
Ross Thompson	0d79c0cebe	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-02-19 22:54:27 -06:00
David Harris	6d405ad69b	Fixed RAM instantiations	2023-02-19 06:31:41 -08:00
David Harris	a194740562	Fixed RAM bugs and refactored with read taking place after clock edge rather than before.	2023-02-17 19:14:38 -08:00
David Harris	9275bfb839	Memory synthesis updates	2023-02-17 15:33:49 -08:00
David Harris	2060683770	Continue fixing memory macros for synthesis	2023-02-17 15:15:37 -08:00
David Harris	3523318acb	Synthesis with memories	2023-02-17 13:51:05 -08:00
Ross Thompson	27f6552315	keep this commit off of cvw.	2023-02-16 11:05:24 -06:00
James Stine	744991bd5a	Update if-then-else for ram items	2023-02-15 18:12:12 -06:00
Kevin Kim	c59dfc1e30	fixed typo in LZC	2023-02-11 19:59:03 -08:00
David Harris	aae035226f	Merged with memories	2023-02-02 14:50:46 -08:00
David Harris	99d179dd3e	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00