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Author SHA1 Message Date
Kip Macsai-Goren
26e8b85111 added beginning of a ZBS instruction module to the ALU. Control signals still needed 2023-02-01 21:31:25 -08:00
Ross Thompson
a8afdf1741 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-01 19:24:10 -06:00
David Harris
93f57402df Removed O2 from fir Makefile to be consistent with lab. 2023-02-01 15:43:52 -08:00
David Harris
c214a9e8fc
Merge pull request #45 from stineje/main 
Update ram2 and other memories and associated wrappers
 2023-02-01 15:06:30 -08:00
James Stine
6ce80b6b8a Update ram2 and other memories and associated wrappers 2023-02-01 17:03:48 -06:00
Ross Thompson
0035579553 Minor branch predictor bug fix. 2023-02-01 10:59:38 -06:00
Ross Thompson
2a5b6408f2 Removed unused signal. 2023-02-01 10:27:58 -06:00
David Harris
129380db0b Fixed typo in DC setup for memories 2023-02-01 05:49:30 -08:00
David Harris
c9b56f9acc Only add memory libraries when targeting 28nm 2023-02-01 05:06:56 -08:00
David Harris
73b29e1f71
Merge pull request #36 from davidharrishmc/dev 
RV32imc configuration
 2023-02-01 04:44:36 -08:00
David Harris
0280942563 Fixed merge conflict to get synthesis working again 2023-02-01 04:43:57 -08:00
David Harris
838bb21077
Merge pull request #43 from mmasserfrye/main 
ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
 2023-02-01 04:13:37 -08:00
Ross Thompson
c3e3afe398 Minor change to btb. 2023-02-01 00:24:54 -06:00
Madeleine Masser-Frye
ad6d7eb5e2 added memories (not tested) 2023-02-01 06:08:27 +00:00
Ross Thompson
a9624b1413 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-01 00:01:14 -06:00
Madeleine Masser-Frye
c78adbb8e7 increased bpred size to (2^) 5 2023-02-01 05:51:31 +00:00
Madeleine Masser-Frye
02a1432c46 updated synth makefile to change all relevant 
ram ranges to 1FF
 2023-02-01 05:40:35 +00:00
Madeleine Masser-Frye
a8ed39ecbe Merge branch 'main' of https://github.com/mmasserfrye/cvw 2023-02-01 05:23:04 +00:00
Ross Thompson
8a6eaa23cc Minor optimization to btb. 2023-01-31 22:03:51 -06:00
David Harris
c666015c56 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-31 14:40:19 -08:00
David Harris
9270285f3a Removed student solution to fir 2023-01-31 14:40:12 -08:00
David Harris
8d242d47dd
Merge pull request #42 from ross144/main 
Scripts to run imperas
 2023-01-31 14:31:10 -08:00
Ross Thompson
81b280576f Updates to RAS. 2023-01-31 15:17:32 -06:00
Ross Thompson
fc2e3fed91 Simplified RAS. 2023-01-31 14:54:05 -06:00
Ross Thompson
a89f9dc92c RAS file name was spelled wrong. 2023-01-31 14:35:05 -06:00
Ross Thompson
92fc532b82 Created scripts to install imperas and run a single test using imperas. 2023-01-31 13:51:05 -06:00
David Harris
ce98083ffd
Merge pull request #41 from ross144/main 
Merged imperas branch into main. Remove old branch when pull request accepted.
 2023-01-31 11:35:50 -08:00
Ross Thompson
d821105697 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-01-31 13:04:41 -06:00
Ross Thompson
c9c4f63c18 Fixed remaining bugs in the imperas merge. 2023-01-31 13:04:26 -06:00
Ross Thompson
026071e247 Merge branch 'imperas' 2023-01-31 12:46:22 -06:00
Ross Thompson
5a770f148c Minor bug fix in gshare. 2023-01-31 10:45:32 -06:00
Ross Thompson
ad0a0f0d51 Renamed signals in RAS. 2023-01-31 10:44:11 -06:00
David Harris
e96ba254eb Removed output delay in synthesis 2023-01-31 04:37:23 -08:00
Ross Thompson
0e3c77bed3 Found small bug in gshare. 2023-01-31 00:17:49 -06:00
Ross Thompson
939095615f Fixed parameterization in testbench. 2023-01-31 00:11:01 -06:00
Ross Thompson
8feac6d242 Parameterized testbench branch predictor preload. 2023-01-31 00:08:11 -06:00
Ross Thompson
238c4d14a9 More branch predictor cleanup. 2023-01-30 23:55:52 -06:00
Ross Thompson
80f50f10d3 Improved signal names. 2023-01-30 23:51:04 -06:00
Ross Thompson
a15889e0aa Major cleanup of branch predictor. 2023-01-30 23:37:34 -06:00
Ross Thompson
42828e6ec4 Simplified gshare. 2023-01-30 19:27:18 -06:00
Ross Thompson
4cbefd9834 Minor gshare optimization. 2023-01-30 18:13:12 -06:00
David Harris
1121ff0fa7 Restored top-level modules without import statements 2023-01-30 12:54:40 -08:00
David Harris
4a4be04530 Moved out version of wally using package because synthesis isn't working yet 2023-01-30 12:48:52 -08:00
David Harris
a2f66313ea Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-01-30 11:00:51 -08:00
David Harris
f15e7ce380 Updated Questa to 2022.4_2. 2023-01-30 11:00:41 -08:00
Madeleine Masser-Frye
5625996f44
Merged conflicts in fixing synthesis config/hdl writing (#40) 
* Fixed writing config files for synth sweeps

* cleaned up comments

* Fixed copying hdl subdirectories and referencing the correct config files for modified features

* improved readability for synth scripts

* cleans run directory post run and leaves copy of wally-config
 2023-01-30 20:54:19 +02:00
Madeleine Masser-Frye
03c13b6034 Merge branch 'main' of https://github.com/mmasserfrye/cvw 2023-01-30 18:51:05 +00:00
David Harris
d38f4a040c
Merge pull request #38 from ross144/main 
Imperas found bug with hptw
 2023-01-30 10:10:41 -08:00
Ross Thompson
cc48cdc97b Imperas found a real bug in virtual memory. 
If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.

Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
 2023-01-30 11:47:51 -06:00
Ross Thompson
f667843ce9 Merge branch 'main' of github.com:ross144/cvw 2023-01-29 22:39:53 -06:00